Xscape Photonics is redefining how the world moves and processes information—at the speed of light.

We’re building next-generation photonic technologies that push the boundaries of performance, scalability, and efficiency for the most demanding compute and communication systems. By blending deep scientific innovation with real-world impact, Xscape is unlocking new possibilities across AI, data centers, and advanced optical systems.

With a world-class team of researchers, engineers, and industry leaders, Xscape is entering a powerful growth phase. This is a unique opportunity to help carry foundational photonic technology from the lab into large-scale deployment.

If you’re driven by hard problems, excited by first-principles thinking, and motivated by seeing your work shape the future, we’d love to meet you.

At Xscape Photonics, we’re not just building photonics—we’re engineering the future with light.

Role Overview

We are seeking an experienced PIC Test Manager with deep expertise in wafer-level

optical and electrical test for Photonic Integrated Circuits (PICs). This role will own the

test strategy and execution across the full product lifecycle—from early silicon bring-

up through high-volume manufacturing (HVM).

The ideal candidate is a recognized technical authority in test architecture, PIC

Design-for-Test (DFT), yield learning, and factory scalability, with proven leadership

in driving robust wafer-level test solutions across multiple technology nodes and product

families.

Key Responsibilities

Wafer-Level Test Strategy & Architecture

 Define and own the wafer-level PIC test roadmap across multiple product lines and technology platforms, all the way to high-volume manufacturing (HVM).

 Architect scalable, high-throughput optical + electrical wafer probe solutions,

balancing alignment accuracy, probe stability, and test time.

 Establish release criteria, guard-banding strategy, and wafer test coverage

models aligned with product requirements.

First Silicon Bring-Up & Test Content Development

 Lead first-silicon bring-up efforts, including test content definition, limit setting,

and characterization flows.

 Drive rapid yield-learning loops in partnership with design, process integration,

and fabrication teams.

 Enable fast debug and iteration during early node transitions and new platform

ramps.

DFT & PDK Collaboration

 Influence PIC Design-for-Test features and PDK structures to improve wafer-level

scalability, including:

o On-chip monitors

o Loopback paths

o Test waveguides

o Calibration structures

 Partner with design teams to embed manufacturable test hooks early in the

development cycle.

Yield Ownership & Data-Driven Analysis

 Own wafer-level yield, parametric distributions, and systematic defect learning.

 Perform advanced spatial analytics using wafer maps and statistical methods to

separate random vs systematic process issues.

 Lead root-cause investigations related to coupling variation, lithography bias, and

process drift.

Manufacturing Readiness & Factory Scale-Up

 Establish golden wafer / golden die methodologies for production stability and

tool correlation.

 Partner with foundries and OSATs to qualify wafer-level optical probe

infrastructure.

 Drive successful transfer of test flows into volume manufacturing environments

with strong cross-tool correlation.

Technical Leadership & Team Development

 Serve as the technical escalation point during yield crises and manufacturing

transitions.

 Mentor and develop senior engineers, setting engineering standards and best

practices across wafer-level test programs.

 Multiply organizational impact through scalable infrastructure, DFT influence, and

test standardization.

Qualifications

Required

 10+ years of experience in PIC test engineering, wafer-level probing, or

photonics manufacturing test.

 Proven ownership of wafer-level optical/electrical test strategy from R& D through

HVM.

 Expertise in:

o Wafer-level optical probing

o Probe card qualification

o Yield learning and spatial analysis

o Test time optimization

o Foundry engagement and factory transfer

Preferred

 Experience influencing PIC DFT and collaborating closely with PDK development

teams.

 Strong background in high-volume semiconductor or photonics manufacturing

ecosystems.

 Demonstrated leadership in scaling test infrastructure across multiple nodes and

product families.