We are seeking a Physical Design Lead to own and drive the end-to-end physical implementation of testchips and high-speed interface subsystems such as DDR/LPDDR PHY, HBM PHY, and UCIe from netlist through tape-out ready GDSII on leading-edge process nodes. This is a technical lead role: candidate is expected to take full ownership of implementation scope, mentor junior PD engineers, define methodology, and drive cross-functional coordination with RTL design, DFT, analog/custom layout, and verification teams. Seniority level to be determined by experience.

Key Responsibilities

• Own end-to-end physical implementation of assigned testchip or high-speed interface subsystem(DDR/LPDDR, HBM, UCIe, or equivalent): floorplanning, power grid design, placement, clock tree synthesis(CTS), routing, and chip finishing through to GDSII stream-out.

• Coordinate timing closure across all functional modes and PVT corners with the dedicated full-chip STAowner; provide timing-aware physical implementation decisions, flag routing and placement contributors to timing degradation, and execute physical ECOs as directed.

• Lead chip-level or subsystem-level floorplan definition: partition boundaries, I/O ring assembly, hard IP (PHY, memory, custom analog) placement, power domain planning, and bump/pad assignment; balance area, routability, and signal-integrity constraints.

• Define and enforce the physical design methodology and flow for the team: synthesis-to-P&R handoff conventions, ECO management, signoff checklists, and documentation standards; develop and maintain flow automation scripts for regression, reporting, and incremental ECO runs.

• Drive power integrity sign-off: static and dynamic IR-drop analysis (Redhawk/Voltus or equivalent), EM rule compliance, power strapping strategy, and decap insertion; collaborate with circuit and layout teams to resolve violations.

• Coordinate physical verification closure (DRC/LVS/ERC/Antenna) using Calibre or equivalent, including custom analog and mixed-signal IP integration; manage foundry rule deck updates and waiver documentation.

• Interface with RTL designers, DFT engineers, and analog/custom layout engineers to align on design constraints, resolve integration issues, and ensure clean handoff at each project milestone; represent physical design in architecture and tapeout readiness reviews.

• Mentor and technically guide junior and mid-level physical design engineers; review their floorplans and closure strategies; provide actionable feedback and escalate risks proactively to the program lead.

Required Qualifications

• BS/MS in Electrical/Electronic Engineering, Computer Engineering, or related field.

• 7–10+ years of hands-on physical design experience in ASIC or IP design environments, with at least 2–3 years in a technical lead or block owner capacity; multiple tape-outs at sub-10nm process nodes required.

• Demonstrated end-to-end ownership of a full testchip or major subsystem (ideally a high-speed interface block such as DDR/LPDDR PHY, HBM PHY, SerDes, or UCIe) from netlist to GDSII, including full sign-offresponsibility.

• Expert-level proficiency in P&R tools: Cadence Innovus or Synopsys Fusion Compiler / ICC2; working knowledge of STA tools (PrimeTime or Tempus) and IR/EM analysis tools (Redhawk or Voltus).

• Solid understanding of advanced-node physical design constraints: FinFET/GAA design rules, local interconnect, self-aligned multi-patterning (SAMP/SADP), metal density, and via-pillar requirements at 7nmand below.

• Ability to collaborate effectively with analog/custom layout engineers on hard IP integration, pin assignment, and parasitic-aware routing constraints.

Preferred / Nice-to-Have Experience

• Knowledge of MMMC STA, constraint authoring (SDC), and timing ECO generation; able to diagnose and engage on critical-path violations in collaboration with the STA owner.

• Scripting proficiency in Tcl and Python for flow automation, reporting dashboards, and ECO management; ability to write maintainable scripts that other engineers can adopt independently.

• Ability to read transistor-level schematics and communicate layout-sensitive constraints with circuit designers.

• Hands-on physical implementation experience on DDR5/LPDDR5/LPDDR5X, HBM2E/HBM3, or UCIe PHY subsystems, including awareness of timing-critical DQ/DQS paths, ZQ calibration logic placement, and bump map / RDL routing for 2.5D/3D integration.

• Experience with multi-die or chiplet integration: die-to-die bump planning, interposer-level routing constraints, and power delivery co-design between base die and HBM stack.

• Exposure to low-power design implementation: UPF/CPF power intent integration, multi-voltage domain routing, power switch cell placement, and level-shifter insertion in P&R.

• Support post-silicon bring-up and failure analysis where physical implementation is a suspected contributor; correlate silicon measurements against IR-drop, EM, and timing sign-off data.