
NeuReality delivers AI infrastructure that increases GPU utilization and lowers latency, power, and cost for large-scale inference. It combines the NR1 Network Addressable Processing Unit (NAPU) hardware with NR-NEXUS, a production-grade inference-serving OS that unifies networking and orchestration so the data path and control plane operate as one system. The platform productizes and integrates fragmented open-source inference frameworks and targets cloud, edge, and hyperscale deployments. NeuReality's solution reduces reliance on CPUs and enables inference and training clusters to scale without adding racks, improving throughput and energy efficiency.

NeuReality delivers AI infrastructure that increases GPU utilization and lowers latency, power, and cost for large-scale inference. It combines the NR1 Network Addressable Processing Unit (NAPU) hardware with NR-NEXUS, a production-grade inference-serving OS that unifies networking and orchestration so the data path and control plane operate as one system. The platform productizes and integrates fragmented open-source inference frameworks and targets cloud, edge, and hyperscale deployments. NeuReality's solution reduces reliance on CPUs and enables inference and training clusters to scale without adding racks, improving throughput and energy efficiency.
We are looking for a hands-on, experienced Physical Design Engineer to join us and help define and implement NeuReality’s next-generation AI SoC in an advanced technology node
You will play a key role in building and leading our physical design team, developing flows and methodologies, and driving the full RTL-to-GDSII implementation and signoff for one of the most advanced SoCs in the industry.
What You’ll Do
· Take part in shaping methodology and best practices in advanced technologies
· Drive end-to-end implementation: synthesis, P&R, timing closure, and signoff
· Collaborate closely with architecture and design teams on timing, floorplaning, partitioning, and power specification
· Define and optimize static timing constraints, area, and power goals at block and top levels
· Take part in flow development and automation to improve efficiency and quality of results
Requirements:
· BSC/MSC in Electrical/Computer Engineering
· 5+ years’ experience with RTL2GDS flow
· Deep understanding on STA principals, synthesis, and P&R flow
· Solid experience in physical verification and advanced process nodes
Advantages:
· Top level implementation and signoff
· Experience with DFT
· Managerial experience