SEMIFIVE is a leading custom silicon design partner, positioning itself as the new global hub for custom silicon. Founded in 2019 in Seoul, South Korea, the company leverages over 20 years of Korean…
SEMIFIVE is a leading custom silicon design partner, positioning itself as the new global hub for custom silicon. Founded in 2019 in Seoul, South Korea, the company leverages over 20 years of Korean…
SEMIFIVE is a leading design solution partner that bridges global customers with Samsung Foundry. The organization focuses on delivering cutting-edge semiconductor design solutions to address complex challenges. SEMIFIVE is renowned for its innovation and collaborative approach, empowering semiconductor advancements globally. The company strives to enable groundbreaking technologies by providing high-quality design services.
Role Description
This is a full-time, on-site position located in Bengaluru for a Physical Design Engineer. The role involves working on the implementation of physical design flows, performing physical verification, and collaborating on logic and circuit design projects. The engineer will be responsible for ensuring the quality of designs, overseeing physical implementation, and working closely with cross-functional teams to meet project goals.
Qualifications:
Startup jobs. A lot of them.
Your next opportunity is in here somewhere. Sign up to explore 52,000+ startups and their open roles. No spam. No gamification. Just jobs.
52,000+
Startups
58,000+
Open Roles
2,400+
New This Week
Technical Writer
Part-timeMunich, DE
Part-time • Munich, DE
DevOps Engineer
Part-timeHamburg, DE
Part-time • Hamburg, DE
DevOps Engineer
Full-timeHaifa
Full-time • Haifa
AI Researcher
Full-timeManchester, GB
Full-time • Manchester, GB
Mobile Developer
Part-timeNiš, RS
Part-time • Niš, RS
Machine Learning Engineer
InternshipNovi Sad, RS
Internship • Novi Sad, RS
4–10 years of hands-on experience in
Physical Design
from
RTL to GDSII
Strong expertise in
floorplanning, power planning, placement, CTS, routing, and signoff
Proven experience in
advanced technology nodes
(e.g., 8nm and below)
Solid understanding of
timing closure
(STA), including setup/hold, SI, and ECO flows
Experience with
low-power design techniques
(UPF, multi-voltage, power gating)