• ASIC design flow and direct experience with ASIC design in sub-20nm technology nodes.
• Digital design and experience with RTL design in Verilog/SystemVerilog & Synthesis.
• Expertise in RTL QA flows like Lint, CDC/RDC, LEC, Synthesis etc.
• Modern SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulation.
• Low power digital design and analysis.
• Experience with AMS designs and running Equivalence checking using Synopsys ESP.
• Support the next generation IP validation.
• TCL, Perl, Python scripting.
• Strong verbal and written communication skills.
• Should have experience working in geographically dispersed team and should be a strong team player.

Qualification

• Btech /Mtech Electronics Engineering / VLSI