Memory Layout Engineer
Location: Bengaluru, India (On-site)
Domain: Semiconductor / Memory IP Design
Company Description
M31 Technology Corporation is a professional silicon intellectual property (IP) provider. With its headquarters in Hsinchu, Taiwan, M31 has substantial experiences in IP development, IC design, and electronic design automation fields. They specialize in providing high-speed interface IPs, memory compilers, and standard cell library solutions. For more information, please visit http://www.m31tech.com.
Role Overview
We are seeking an experienced Memory Layout Engineer to lead the physical design and delivery of advanced memory IPs, including SRAM, ROM, Register Files, and CAMs, at advanced technology nodes.
This role plays a critical part in delivering high-quality memory IPs with best-in-class Performance, Power, Area (PPA), yield, and foundry compliance.
This is a high-impact role contributing to next-generation memory solutions used by global customers across diverse applications.
Key Responsibilities
- Lead end-to-end memory layout design and floorplanning for advanced technology nodes
- Design and integrate bitcells, periphery circuits, decoders, sense amplifiers, and memory arrays
- Optimize layouts for PPA, routing efficiency, power integrity, and EM/IR reliability
- Deliver DRC, LVS, and DFM-clean GDS along with complete IP collateral
- Collaborate closely with circuit design, CAD, verification, and SoC integration teams
- Drive layout innovations to achieve aggressive density and performance targets
- Support memory compiler development and customer-specific customization
- Ensure compliance with foundry rules and reliability requirements
Required Skills & Qualifications
- Hands-on experience in Memory Layout design
- Strong expertise in Cadence Virtuoso and Calibre verification tools
- Deep understanding of memory architectures (SRAM, ROM, DRAM, CAM)
- Solid knowledge of design rules, parasitic effects, and physical verification flows
- Experience in layout automation and scripting (SKILL, TCL, Python is a plus)
- Strong debugging and problem-solving skills for routing, EM/IR, and DRC challenges
- Proven experience working in cross-functional teams
- Ability to mentor junior engineers is a plus
Success Criteria
- Delivery of high-density, high-performance memory IPs
- Achieving PPA and yield targets across PVT corners
- Smooth and reliable integration into customer SoCs
- First-pass silicon success and foundry compliance
Why Join Us
- Work on cutting-edge technology nodes
- Influence next-generation memory IP development
- Collaborate with global semiconductor leaders
- High-visibility role with strong growth potential
