
Chip Smart Technologies provides semiconductor design services to build advanced telecom and photonics chips. It focuses on ASIC design with mixed-signal IP, firmware solutions for large telecom systems, RF and photonic ICs, and FPGA capabilities, supported by RTL coding and verification. The company operates as a B2B services firm working with telecoms, semiconductor designers, and embedded systems developers, leveraging standard EDA tools like Cadence, Synopsys, and Mentor Graphics. Its product portfolio includes analog and mixed-signal functional blocks, I/O interfaces, RF blocks, and embedded systems development, including configurable 5G AI Accelerator architectures to boost network performance. Chip Smart Technologies aims to be a leading global chip design company delivering high-quality semiconductor solutions that advance technology and improve lives.

Chip Smart Technologies provides semiconductor design services to build advanced telecom and photonics chips. It focuses on ASIC design with mixed-signal IP, firmware solutions for large telecom systems, RF and photonic ICs, and FPGA capabilities, supported by RTL coding and verification. The company operates as a B2B services firm working with telecoms, semiconductor designers, and embedded systems developers, leveraging standard EDA tools like Cadence, Synopsys, and Mentor Graphics. Its product portfolio includes analog and mixed-signal functional blocks, I/O interfaces, RF blocks, and embedded systems development, including configurable 5G AI Accelerator architectures to boost network performance. Chip Smart Technologies aims to be a leading global chip design company delivering high-quality semiconductor solutions that advance technology and improve lives.
Industry experience in Memory Leafcell layout design
Strong understanding of memory architectures and performance optimization
Strong grasp of FinFET technology
Hands-on experience in memory domain: characterization, design, and validation
Proficient in writing Spice decks, stimulus, and test vectors
Experience with fast simulation tools and waveform vowere
Kriowledge of layout parasitic extraction and deep submicron technology challenges
Good at LVS/DRC debugging skills and other verifications for lower technology nodes
Familiar with EDA tools like Cadence SKILL scripting and automation for compiler Rows and layout reuse
Familiarity with NMDL + CCST libraries
Understanding layout effects on the circult such as speed, capacitance, power and area etc..
Capable of generating libs and performing QA sign-off
Ability to understand design constraints and implement high-quality layouts.
Good people siills and critical thinking abilities to resolve the issue technically, and professionally.
Minimum Educational Qualification: Educational Bachelor's, Electrical or Electronics Engineering or equivalent Rennirements