Representative projects

• Optimize operation sequences to maximize Sohu's computational resources for specific transformer architectures such as Llama 4.
• Research and implement efficient memory management for KV cache sharing and prefix optimization
• Develop algorithms for continuous batching and batch interleaving to improve throughput and/or latency
• Research and implement model-specific inference-time acceleration algorithms such as speculative decoding, tree search, KV cache sharing, priority scheduling, etc by interacting with the rest of the inference serving stack
• Research and implement structured decoding and novel sampling algorithms for reasoning models

You may be a good fit if you have

• Co-design expertise across both SW and HW domains
• Strong software engineering skills with systems programming experience
• Deep knowledge of transformer model architectures and/or inference serving stacks (vLLM, SGLang, etc.)
• Strong mathematical skills, esp. in linear algebra
• Ability to reason about performance bottlenecks and optimization opportunities
• Experience working cross-functionally in diverse software and hardware organizations

Strong Candidates May Also Have Experience With

• Experience with hardware accelerators, ASICs, or FPGAs
• Experience with Rust programming language
• Deep expertise in ML systems engineering and hardware/software co-design with demonstrated impact (contributions to open-source projects or published papers)
• Track record of optimizing large co-designed SW / HW systems

Benefits

• Full medical, dental, and vision packages, with generous premium coverage
• Housing subsidy of $2,000/month for those living within walking distance of the office
• Daily lunch and dinner in our office
• Relocation support for those moving to West San Jose

Compensation Range

• $150,000 - $275,000

How We’re Different Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in West San Jose, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.