Blueberry Semiconductors Pvt. Ltd. is a design service startup specializing in ASIC/SoC and embedded product engineering, empowered by Machine Learning, Industrial IoT, and Artificial Intelligence. With over 20 years of SoC design experience and more than 300 successful tape-outs, the company serves clients globally across aerospace, automotive, AI, 5G, memory, industrial, medical, consumer, smart home, and data center sectors. Their flexible business model includes staff augmentation, onsite/offsite ODC, and Build-Operate-Transfer (BoT) engagements. Blueberry has a stable and growing customer base with long-term engagements, focusing on accelerating time-to-market through innovative solutions and a strong team of 120+ members with 100+ years of collective experience.
Blueberry Semiconductors Pvt. Ltd. is a design service startup specializing in ASIC/SoC and embedded product engineering, empowered by Machine Learning, Industrial IoT, and Artificial Intelligence. With over 20 years of SoC design experience and more than 300 successful tape-outs, the company serves clients globally across aerospace, automotive, AI, 5G, memory, industrial, medical, consumer, smart home, and data center sectors. Their flexible business model includes staff augmentation, onsite/offsite ODC, and Build-Operate-Transfer (BoT) engagements. Blueberry has a stable and growing customer base with long-term engagements, focusing on accelerating time-to-market through innovative solutions and a strong team of 120+ members with 100+ years of collective experience.
JD for a Physical Design Lead (Sub-3 nm, TSMC, 8–10 yrs, Synopsys / Cadence)
Job Title
Physical Design Lead – Advanced Node (Sub-3 nm, TSMC)
Location:
Bangalore
Experience
: 8+ to 12 years
Job Mode
: Full Time
Position Summary
Lead end-to-end physical implementation and signoff for complex SoC blocks or subsystems at advanced nodes (5 nm, 3 nm and below), using Synopsys and/or Cadence tool flows, preferably, targeting TSMC technologies. Own PPA and signoff closure for
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multi-million instance designs and drive successful production tape-outs while leading and mentoring a local PD team.
Key Responsibilities
· Own complete physical design flow (floor planning, power planning, placement, CTS, routing, optimization, ECOs) for
high-complexity blocks/subsystems with multi-million standard-cell instances (10M+ gate equivalent)
across multiple clock and power domains.
· Drive timing signoff and closure using
Synopsys PrimeTime (PT) and/or Cadence Tempus
in MMMC environments, including CPPR, AOCV/POCV, on-chip variation, and path-based analysis. Knowing Power aware timing analysis is a plus.
· Define and implement
Power Delivery Network (PDN)
at block and top level: power grid topology, straps, via ladders, mesh/tree hybrids, and decap strategy; coordinate with package/board power-integrity teams.
· Own
IR drop and EM signoff
(static and dynamic) using tools such as
Ansys RedHawk, Cadence Voltus or equivalent
; debug hotspots and drive fixes to meet voltage droop, current-density, and reliability specs at advanced TSMC nodes.
· Manage physical verification and manufacturability signoff (DRC, LVS, ERC, antenna, density/fill, SI, reliability) using foundry decks and tools such as
Mentor Calibre, Cadence Pegasus
.
· Implement and optimize
low-power design techniques
: multi-VDD domains, UPF/CPF power intent, power/clock gating, retention, level shifters, isolation cells, and state retention aligned with TSMC low-power guidelines.
· Interface with
TSMC PDKs, reference flows and tape-out processes
, ensuring adherence to design rule manuals and signoff checklists; prepare and review signoff reports for tape-out.
· Provide
technical leadership
to PD engineers: task planning, code and constraint reviews, methodology enforcement, and cross-team coordination with RTL, DFT, STA, PDN, packaging, and global counterparts.
Required Skills and Experience
· 8–10 years of
ASIC physical design experience
with multiple
production tape-outs at 7/5/3 nm or below
, preferably on
TSMC N7/N5/N3/N2
nodes.
· Proven ownership of SoC blocks/subsystems of
multi-million standard-cell instances / multi-tens-of-million gate equivalent
, including timing, congestion, power, and area closure.
· Strong hands-on experience with one or more of the following tool chains:
o
Synopsys flow:
Design Compiler / Fusion Compiler or ICC2, PrimeTime, RedHawk/PrimePower or equivalent.
o
Cadence flow:
Genus, Innovus, Tempus, Voltus.
· Deep understanding of
advanced-node challenges
: complex DRC, EUV layers, parasitics, large MMMC space, variation and derates, and their impact on timing, IR, noise, and yield.
· Demonstrated ability in
PDN planning and EMIR closure
, including correlation to silicon where available.
· Strong scripting skills in
Tcl and/or Python
for flow automation, report parsing, and methodology development.
Education and Soft Skills
· B.E./B.Tech or M.E./M.Tech in ECE/EEE/VLSI or related discipline from a recognized institute.
· Excellent communication and collaboration skills to work with cross-site, cross-functional teams; strong ownership mindset and ability to drive issues to closure under aggressive schedules.
