Build formal verification environments/testbenches from scratch and integrate with RTL designs.

Dive deep into microarchitecture specifications, extract verification requirements, and craft formal test plans.

Apply divide-and-conquer, abstraction, and complexity reduction techniques to tackle large designs effectively.

Drive verification to closure with clear sign-off criteria.

Collaborate with design teams and provide early bug detection and root-cause analysis using formal.

Leverage and verify industry-standard protocols (AMBA AXI/AHB/APB, PCIe, USB, I2C, SPI, etc.).

Mentor and coach engineers in formal verification tools, flows, and best practices, building team strength.

What We’re Looking For

2+ years of strong hands-on experience in Formal Verification at the IP level.

Proficiency in System Verilog Assertions (SVA).

Proven track record of building formal verification testbenches from scratch.

Ability to comprehend microarchitecture specs and map them into verification requirements.

Skill in applying formal abstraction, modularization, and scalability techniques.

Mandatory: Hands-on experience with at least one commercial formal verification tool (Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal, OneSpin).

Solid understanding of AMBA protocols and other high-speed/serial protocols.

Strong communication and documentation skills.

Passion for mentoring and enabling engineers to excel in formal verification.