Company Description

Proxelera specializes in advanced semiconductor design services, offering expertise in VLSI, RTL design, verification, FPGA prototyping, and embedded software development. The company supports engineering teams globally in delivering high-quality ASIC/SoC designs with robust functional and formal verification methodologies to ensure optimal outcomes and on-time delivery. Proxelera partners with a diverse range of industries, including AI, automotive, IoT, and wireless connectivity, to deliver seamless silicon design and integration. Known for deep engineering expertise and flexible engagement models, Proxelera is committed to reducing design and schedule risks for its clients. Located in Bengaluru, India, Proxelera provides comprehensive engineering solutions tailored to meet cutting-edge technological demands.

Lead ASIC (SOC & Large Sub Systems) Verification Engineer (UVM / TB Architecture)

Experience: 8 to 15 yrs

Location: Bengaluru

Role Summary:

Own end-to-end verification of complex SoCs or large subsystems blocks. This is a hands-on role from testbench architecture to coverage closure, through tape out and into silicon correlation.

What you’ll do

• Architect and build scalable UVM testbenches from scratch at subsystem or SoC level

• Strong hands-on experience in testbench development

• Define verification strategy and author test plans from specs and micro-architecture

• Develop constrained-random and directed tests, scoreboards, checkers, assertions (SVA), and coverage models

• Drive functional, code, and assertion coverage closure with discipline

• Debug complex issues using waveforms, logs, and root-cause analysis

• Lead SoC-level verification: IP integration, coherency, low-power modes, resets/boot, and performance validation

• Work closely with RTL, architecture, DFT, and firmware teams

• Support silicon bring-up and pre-/post-silicon correlation

Must-have Skills

• 8+ years of hands-on ASIC (SOC & Large Sub Systems) verification (FPGA / emulation experience does not count)

• Strong TB Architecture ownership — design, reuse strategy, scalability, and maintainability

• Multiple production ASIC tapeouts with SoC or large subsystem ownership

• Expert in SystemVerilog, UVM, SVA, and constrained-random methodologies

• Deep experience with AXI/ACE, DDR, PCIe, coherency, memory and interrupt fabrics

• Proven strength in test planning, stimulus strategy, checkers/scoreboards, and closure execution

• Excellent debug skills across simulation and silicon correlation

Role Description (Additional)

This is a full-time, on-site role for a Lead ASIC Verification Engineer based in Bengaluru . The role focuses on leading the verification of complex SoC and large subsystems using UVM and developing testbench architectures . Responsibilities include guiding functional verification methodologies, debugging RTL designs, collaborating with cross-functional teams, and optimizing validation workflows.

Qualifications

• Strong experience in RTL Design and in-depth knowledge of design methodologies

• Expertise in Functional Verification and Validation techniques, with a focus on UVM and testbench development

• Proficient in debugging complex designs to identify and resolve issues efficiently

• Familiarity with industry-standard practices, including compliance

• Proven ability to lead verification teams and implement best verification practices

• Excellent analytical, communication, and documentation skills

• Preferred: Bachelor’s or Master’s degree in Electrical Engineering or a related field, with prior experience in SoC/ASIC design and verification