What you'll do:

• Develop and Utilize Transaction-Level Models (TLMs): Design, adapt, and maintain high-quality TLMs (primarily using C++ / SystemC) for peripherals, memory subsystems, and other SoC components to build comprehensive virtual platforms centered around Codasip RISC-V IPs.
• Drive SoC Integration for Codasip RISC-V IPs: Employ TLMs to integrate Codasip RISC-V IPs with diverse external components, enabling robust in-situ IP evaluation and facilitating rapid prototyping of customer-representative SoCs.
• Enhance RISC-V IP Evaluation in SoC Contexts: Advance our Exploration Framework by integrating sophisticated TLM-based environments to showcase the performance and capabilities of Codasip RISC-V cores under realistic SoC workloads.
• Create and Refine SoC-Level Mocking Capabilities: Contribute to our initiatives for developing TLM-based mocking of external modules. This will allow defining descriptive input/output and processing behaviors, enabling early software development on virtual platforms incorporating Codasip RISC-V IPs.
• Model Memory Subsystems for RISC-V SoC Performance Analysis: Utilize TLMs to accurately model various memory interfaces (e.g., DDRx, LPDDRx) and hierarchies (caches), simulating their impact on overall system throughput and IP behavior within an SoC.
• Analyze and Optimize RISC-V based SoC Performance: Leverage TLM-based simulations to gain deep insights into IP behavior within an SoC, identify performance characteristics, and provide actionable feedback to IP design teams and customers.
• Support Codasip IP Deployment: Act as a key resource for our IP teams and field application engineers, providing expert guidance and utilizing TLM environments to help demonstrate, enhance, and ensure successful integration of Codasip IPs into customer SoCs.

What you need:

• Proficiency in C++ and ideally System C: Essential for developing, adapting, and utilizing Transaction-Level Models (TLMs), mocking external components, and integrating IPs within SoC simulation environments.
• Solid Understanding of SoC Architecture and Integration: Knowledge of how different components (CPU cores, particularly RISC-V, buses, memory, peripherals, accelerators) interact within an SoC is crucial for effective TLM application.
• Hardware Knowledge (Communication & Memory): Understanding of common bus protocols (e.g., AMBA AXI, TileLink) and memory subsystem concepts (latency, bandwidth, caching, DDRx/LPDDRx) is needed for accurate modeling and integration.
• Foundational Knowledge of Computer Architecture: Familiarity with processor architecture, ideally with exposure to RISC-V, provides necessary context for integrating and evaluating IPs.
• Motivation and Prototyping Mindset: Enthusiasm for working in an R&D and customer-enabling environment, focused on applying modeling and simulation for developing and evaluating new SoC concepts featuring Codasip RISC-V IPs.
• Fluent English: Ability to communicate effectively (both written and spoken) within an international team and with customers.

What you might have:

• Practical Experience with TLM Development or Usage: Proven track record of building or extensively using TLMs for simulation, virtual prototyping, or IP evaluation in an SoC context.
• Experience with Python: Particularly for scripting interactions with simulation frameworks, test automation, or model generation.
• Knowledge of RISC-V Architecture and Ecosystem: Deeper understanding of RISC-V ISA, privilege modes, extensions, and the broader ecosystem.
• Knowledge of Hardware/System Security Concepts: Understanding fundamental security principles relevant to SoC components and their interactions, especially in the context of extensible architectures like RISC-V.
• Familiarity with IP/SoC Standardization: Understanding of industry standards (e.g., related to RISC-V International) or experience contributing to standardization efforts in modeling or interfaces.

What's in it for you?

Join a flexible, open and supportive team full of curious, self-motivated and driven engineers who are keen to explore new ways of doing things, you'll get to work on ultra-modern, cutting-edge products and technology.

As a Codasipper, you will have the freedom to explore original solutions and experiment with new techniques in your role. We believe in cross-departmental awareness and encourage collaboration, allowing you to add value through diversity in your daily work.

So, come aboard and let's architect a future of innovation together! We can't wait to see what you'll achieve at Codasip.

Some useful Links on Codasip:

• Codasip RISC V Processor Solutions
• Design for differentiation: architecture licenses in RISC‑V
• Scaling is Failing - Dr. Ron Black, CEO, Codasip
• Codasip Labs to accelerate advanced technologies
• CHERI Security Technology