Integration and IP Evaluation Engineer | Codasip · Teeming.ai
Codasip
Codasip provides customizable RISC-V processors that let system-on-chip developers tailor compute to specific application needs. It delivers this via Codasip Studio design-automation tools, a catalog…
Codasip provides customizable RISC-V processors that let system-on-chip developers tailor compute to specific application needs. It delivers this via Codasip Studio design-automation tools, a catalog…
Core business: Customizable RISC-V processor IP and processor-design automation tools
Founded: 2014
Headquarters / Operations: Munich (headquartered) with operations in the UK
Tech highlights: Codasip Studio (CodAL), commercial CHERI implementation, automotive-grade cores
Funding signal: Multiple venture investors plus substantial EU grants (reported €119M in awards as of 2025)
Company Overview
Problem Domain
Custom compute architectures, processor security, SoC enablement for embedded, automotive, and edge AI applications.
Founded
2014
Industry
Semiconductor Manufacturing
Tech Stack
CodAL (processor description language)
Codasip Studio
CHERI (commercial implementation)
Amazon S3
Apache 2.4
reCAPTCHA
Funding Track Record
Series A- 2018-12-04
$10M
Participation from Shenzhen Capital Group, Paua Ventures and Western Digital
Seed- 2014-04
$2.8M
- 2025-07-01
€119M (awarded, most to be received)
Reported EU and national grants and equity awards
Investor Signal
“Combination of venture investors (e.g., Credo Ventures, Ventech, Shenzhen Capital Group, Western Digital) and significant EU grant funding”
Founders
What we do
Join the Team
Integration and IP Evaluation Engineer
On-SiteMunich, Bavaria, DE
On-Site • Munich, Bavaria, DE
Related Companies
Company
HQ
Industry
Total Funding
microTECH Global LTD
🇬🇧Maidenhead, GB
Administrative ServicesDeepTechHR and RecruitingManufacturingProfessional Services
-
ScaleFlux
🇺🇸Milpitas, US
Consumer ProductsData and AnalyticsDeepTechHardwareInformation TechnologyInternet ServicesManufacturingSoftware
$287M
Aion Silicon
🇬🇧Reading, GB
Commerce and ShoppingConstructionDeepTechManufacturingReal Estate
-
BITSILICA
🇮🇳Hyderābād, IN
DeepTechManufacturing
-
SiPearl
🇫🇷Maisons-Laffitte, FR
DeepTechHardwareManufacturing
$154M
**Please note this role is primarily open to candidates currently located in, and with working rights to Germany (preferably Munich, Berlin or Dresden).**
Welcome to Codasip
We believe
Codasip
is the most innovative processor solutions company. We take pride in designing and developing cutting-edge, high-performance, and energy-efficient CPU cores from scratch, and our own automated proprietary tools to fully customize them. We give our customers a unique competitive advantage by empowering their system-on-chip developers to build the most innovative products.
As we expand our focus beyond isolated core evaluations, this role is crucial for developing robust SoC integration strategies and driving industry standardization.
You will be at the forefront of applying TLM methodologies to our RISC-V IP portfolio, creating robust virtual prototypes, and enabling early performance analysis. Your work will involve integrating Codasip RISC-V IPs with a variety of SoC components using TLM, and directly supporting our IP teams and customers by providing expert guidance on SoC integration and in-situ evaluation.
What you'll do:
What you need:
What you might have:
Practical Experience with TLM Development or Usage:
Proven track record of building or extensively using TLMs for simulation, virtual prototyping, or IP evaluation in an SoC context.
Experience with Python:
Particularly for scripting interactions with simulation frameworks, test automation, or model generation.
Knowledge of RISC-V Architecture and Ecosystem:
Deeper understanding of RISC-V ISA, privilege modes, extensions, and the broader ecosystem.
What's in it for you?
Join a flexible, open and supportive team full of curious, self-motivated and driven engineers who are keen to explore new ways of doing things, you'll get to work on ultra-modern, cutting-edge products and technology.
As a Codasipper, you will have the freedom to explore original solutions and experiment with new techniques in your role. We believe in cross-departmental awareness and encourage collaboration, allowing you to add value through diversity in your daily work.
So, come aboard and let's architect a future of innovation together! We can't wait to see what you'll achieve at Codasip.
Some useful Links on Codasip:
Codasip RISC V Processor Solutions
Design for differentiation: architecture licenses in RISC‑V
Scaling is Failing - Dr. Ron Black, CEO, Codasip
Codasip Labs to accelerate advanced technologies
CHERI Security Technology
Startup jobs. A lot of them.
Your next opportunity is in here somewhere. Sign up to explore 70,000+ startups and their open roles. No spam. No gamification. Just jobs.
70,000+
Startups
80,000+
Open Roles
4,600+
New This Week
AI Researcher
Full-timeNew York, US
Full-time • New York, US
DevOps Engineer
ContractAustin, US
Contract • Austin, US
Software Engineer
Full-timeTel Aviv
Full-time • Tel Aviv
Technical Writer
ContractRotterdam, NL
Contract • Rotterdam, NL
DevOps Engineer
Part-timeNovi Sad, RS
Part-time • Novi Sad, RS
Product Designer
Full-timeManchester, GB
Full-time • Manchester, GB
Develop and Utilize Transaction-Level Models (TLMs):
Design, adapt, and maintain high-quality TLMs (primarily using C++ / SystemC) for peripherals, memory subsystems, and other SoC components to build comprehensive virtual platforms centered around Codasip RISC-V IPs.
Drive SoC Integration for Codasip RISC-V IPs:
Employ TLMs to integrate Codasip RISC-V IPs with diverse external components, enabling robust in-situ IP evaluation and facilitating rapid prototyping of customer-representative SoCs.
Enhance RISC-V IP Evaluation in SoC Contexts:
Advance our Exploration Framework by integrating sophisticated TLM-based environments to showcase the performance and capabilities of Codasip RISC-V cores under realistic SoC workloads.
Create and Refine SoC-Level Mocking Capabilities:
Contribute to our initiatives for developing TLM-based mocking of external modules. This will allow defining descriptive input/output and processing behaviors, enabling early software development on virtual platforms incorporating Codasip RISC-V IPs.
Model Memory Subsystems for RISC-V SoC Performance Analysis:
Utilize TLMs to accurately model various memory interfaces (e.g., DDRx, LPDDRx) and hierarchies (caches), simulating their impact on overall system throughput and IP behavior within an SoC.
Analyze and Optimize RISC-V based SoC Performance:
Leverage TLM-based simulations to gain deep insights into IP behavior within an SoC, identify performance characteristics, and provide actionable feedback to IP design teams and customers.
Support Codasip IP Deployment:
Act as a key resource for our IP teams and field application engineers, providing expert guidance and utilizing TLM environments to help demonstrate, enhance, and ensure successful integration of Codasip IPs into customer SoCs.
Proficiency in C++ and ideally System C:
Essential for developing, adapting, and utilizing Transaction-Level Models (TLMs), mocking external components, and integrating IPs within SoC simulation environments.
Solid Understanding of SoC Architecture and Integration:
Knowledge of how different components (CPU cores, particularly RISC-V, buses, memory, peripherals, accelerators) interact within an SoC is crucial for effective TLM application.
Hardware Knowledge (Communication & Memory):
Understanding of common bus protocols (e.g., AMBA AXI, TileLink) and memory subsystem concepts (latency, bandwidth, caching, DDRx/LPDDRx) is needed for accurate modeling and integration.
Foundational Knowledge of Computer Architecture:
Familiarity with processor architecture, ideally with exposure to RISC-V, provides necessary context for integrating and evaluating IPs.
Motivation and Prototyping Mindset:
Enthusiasm for working in an R&D and customer-enabling environment, focused on applying modeling and simulation for developing and evaluating new SoC concepts featuring Codasip RISC-V IPs.
Fluent English:
Ability to communicate effectively (both written and spoken) within an international team and with customers.
Knowledge of Hardware/System Security Concepts:
Understanding fundamental security principles relevant to SoC components and their interactions, especially in the context of extensible architectures like RISC-V.
Familiarity with IP/SoC Standardization:
Understanding of industry standards (e.g., related to RISC-V International) or experience contributing to standardization efforts in modeling or interfaces.
