
Tsavorite Scalable Intelligence is revolutionizing enterprise AI with its innovative chiplet technology, enabling scalable and sustainable AI compute solutions. Their products include advanced robotics and multimodal inference systems, designed for high-performance applications such as streaming video intelligence. The company differentiates itself through power-efficient, supply chain optimized solutions that allow for intuitive software deployment without code changes. With a focus on interoperability and an open ecosystem, Tsavorite positions itself as a leader in the AI space, catering to enterprises looking to leverage AI at scale.

Tsavorite Scalable Intelligence is revolutionizing enterprise AI with its innovative chiplet technology, enabling scalable and sustainable AI compute solutions. Their products include advanced robotics and multimodal inference systems, designed for high-performance applications such as streaming video intelligence. The company differentiates itself through power-efficient, supply chain optimized solutions that allow for intuitive software deployment without code changes. With a focus on interoperability and an open ecosystem, Tsavorite positions itself as a leader in the AI space, catering to enterprises looking to leverage AI at scale.
Founded: 2023
Headquarters: Milpitas, California
Product focus: Omni Processing Unit (chiplet-based) + full-stack software (TAOS)
Funding: Series A; reported ~$17.9M total funding
Scalable, energy-efficient AI compute for enterprise and data-center use cases
2023
Data and Analytics
17904977
Aggregate profile lists a Series A of approximately $17.9M.
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About Tsavorite Scalable Intelligence Inc.
Tsavorite Scalable Intelligence is developing the semiconductor industry’s first Omni Processing Unit™ (OPU) —a unified platform that brings together CPU, GPU, Memory and Connectivity in a single device, engineered for the next wave of Agentic AI workloads.
Our goal is to redefine how AI infrastructure meets performance, efficiency, and scale—whether at the Datacenter, Cloud or Edge.
Founded in 2023, Tsavorite is powered by 100+ seasoned engineers and leaders who have built transformative products and companies.
We are moving rapidly from vision to reality, with , engagements spanning the Americas, Europe and Asia, and working prototypes delivered to customers and developers.
We deliver a full-stack solution: from Compilers, ML libraries and Runtime software to a Hardware platform designed to let you run any AI model or workflow—without platform-specific porting constraints.
Join Our Growing Team!
We’re building a world-class team focused on AI silicon and software innovation. Positions are open in the US and in Bangalore (India) .
If you’re ready to help shape the future of AI compute, attach your resume and a brief introduction to jobs@tsavoritesi.com and take the first step toward an exciting career with us.
Note : A minimum of 5 years+ of industry work experience is required to be considered for the below positions.
ML SW Engineer Positions (multiple positions available in the below areas)
ML Backend Compiler Engineers with MLIR, LLVM experience
ML with PyTorch & ONNX ML Framework Experience
ML engineers with expertise in LLMs, CNN, RNN Inference, and Training
ML Runtime Engineers with Level Zero and Scheduler experience
Performance Engineer with in-depth understanding of ML Model Architecture & Computational requirements. Experience with performance analysis tools and methodologies.
ML Engineer – Multimodal AI and Inference : Strong background in deep learning and model deployment with hands-on experience in PyTroch or TensorFlow. Expertise in Model optimization with quantization, pruning, distillation or mixed-precision inference. Practical knowledge of inference engines (vLLM, llama.cpp, ONNX Runtime). Experience in deploying large models locally or on edge devices with limited memory/compute constraints.
AI Applications Engineer with full-stack web application development experience, including proficiency in Front-end frameworks (React, Netx.js,Svelte) and Backend experience with Python(FastAPI/Flask),Node.js, Rust. Experience with interfacing with AI/ML backend via REST or gRPC APIs.
Experience building apps that integrate LLMs, text-to-image, or speech models. Familiarity with multimodal data handling - audio/video streaming, file parsing, camera/mic APIs
· DevOps/Edge AI Engineer strong background in Linux systems engineering and containerization (Docker, Podman, LXC). Experience in deploying AI Inference Services locally or at the edge (llama.cpp, ollama, vLLM, ONNX). Experience with embedded systems or edge AI devices (e.g., Jetson, Coral). Solid understanding of Networking, Security, and firewall configurations for local appliances.
System SW and FW Engineers (multiple positions available)
RTL Design Engineers
Design Verification Engineers (Multiple positions available under each domain)
· Deep expertise and hands-on experience in developing UVM, SV testbench components, Checkers, Scoreboard and Stimulus with 5yr+ experience in IP/sub-system or SoC level verification.
· Experience in defining test plans and developing directed/constrained random tests to achieve Verification Coverag e
FPGA Prototyping (Platform) Lead
· I n this role you will develop FPGA protypes for Tsavorite's Chiplets and SOC using commercially available FPGA prototype platforms/tools
· Experience in handling RTL-to-Bitstream design cycle on million+ gate FPGAs
· Hands-on experience wiwth design partitioning, Verilog coding for FPGA fit.
· Expertise in timing analysis, design optimization for timing convergence and resource utilization
· Familiarity with Intel/Altera Quartus or AMD Vivado design flows
· Expertise in handling standard debugging tools such as ChipScope or custom debug tools
Preferred Experience : Expertise in configuring and bringing up HardIP/embedded ARM Cores.
· FPGA Design experience with any High Speed IO Protocols (PICe, Ethernet,CXL), configuring and bringup of Softcore Processor Microblaze (Xilinx) or Nios (Altera)
Physical Design Verification Engineers
· Hands-on experience with defining methodology and setting up Physical Verification flows for both Block and SoC-level designs
· Expertise in industry standard tools used for physical verification, such as Mentor Calibre, CalibreDRV, V2LVS, etc.
· Exposure to implementation tools like Innovus/ICC2 is a plus.
Physical Design Engineers
· Experience in Physical Design implementation (from RTL to GDS) at Block or SoC designs on advanced process nodes
· Expertise and experience with industry-standard CAD tools from Synopsys, Cadence or Siemens.
· Experience in collaborating with RTL design and Flows teams to drive feasibility studies and converge Block/SoC designs to meet target power, frequency, and area targets.Company Descriptio n