We deliver a full-stack solution: from Compilers, ML libraries and Runtime software to a Hardware platform designed to let you run any AI model or workflow—without platform-specific porting constraints.

Join Our Growing Team!

We’re building a world-class team focused on AI silicon and software innovation. Positions are open in the US and in Bangalore (India) .

If you’re ready to help shape the future of AI compute, attach your resume and a brief introduction to jobs@tsavoritesi.com and take the first step toward an exciting career with us.

Note : A minimum of 5 years+ of industry work experience is required to be considered for the below positions.

ML SW Engineer Positions (multiple positions available in the below areas)

• ML Backend Compiler Engineers with MLIR, LLVM experience

• ML with PyTorch & ONNX ML Framework Experience

• ML engineers with expertise in LLMs, CNN, RNN Inference, and Training

• ML Runtime Engineers with Level Zero and Scheduler experience

• Performance Engineer with in-depth understanding of ML Model Architecture & Computational requirements. Experience with performance analysis tools and methodologies.

• ML Engineer – Multimodal AI and Inference : Strong background in deep learning and model deployment with hands-on experience in PyTroch or TensorFlow. Expertise in Model optimization with quantization, pruning, distillation or mixed-precision inference. Practical knowledge of inference engines (vLLM, llama.cpp, ONNX Runtime). Experience in deploying large models locally or on edge devices with limited memory/compute constraints.

• AI Applications Engineer with full-stack web application development experience, including proficiency in Front-end frameworks (React, Netx.js,Svelte) and Backend experience with Python(FastAPI/Flask),Node.js, Rust. Experience with interfacing with AI/ML backend via REST or gRPC APIs.

  Experience building apps that integrate LLMs, text-to-image, or speech models. Familiarity with multimodal data handling - audio/video streaming, file parsing, camera/mic APIs

• ·  DevOps/Edge AI Engineer strong background in Linux systems engineering and containerization (Docker, Podman, LXC). Experience in deploying AI Inference Services locally or at the edge (llama.cpp, ollama, vLLM, ONNX).  Experience with embedded systems or edge AI devices (e.g., Jetson, Coral). Solid understanding of Networking, Security, and firewall configurations for local appliances.

System SW and FW Engineers (multiple positions available)

• Systems Platform Engineer with strong knowledge of Linux kernels, IPC/System V, POSIX libraries, multi-threaded SW and process management.
• Systems Engineer with experience in writing device driver for Memory, Control Plane and Cluster Management, with excellent knowledge of Linux kernels, IPC/System V, Memory management and distributed systems, Linux High availability, and NUMA.
• Systems SW Engineer with experience in developing health monitoring, Linux drivers, and memory checker debug frameworks.
• Systems SW Engineer with Experience in cluster management software and device discovery protocols like PAXOS, NCCL, RCCL, or any other distributed device discovery
• Firmware Engineer with experience in writing device drivers for RDMA, RoCE v2, Ethernet, CXL, and other proprietary interfaces.

RTL Design Engineers

• Hands-on experience with micro-architecture and RTL development of ARM CPU Processors or high-speed custom ASICs/Accelerators .
• RTL design expertise w ith any one of - Cache controllers, IO interfaces (PCIe, CXL, Ethernet), UCIe, Memory Controllers, Display, and Video Encoding/Transcoding IP designs .

Design Verification Engineers (Multiple positions available under each domain)

· Deep expertise and hands-on experience in developing UVM, SV testbench components, Checkers, Scoreboard and Stimulus with 5yr+ experience in IP/sub-system or SoC level verification.

· Experience in defining test plans and developing directed/constrained random tests to achieve Verification Coverag e

• CPU: Strong Arch knowledge in ARM Subsystems(CPUSS), including CMN, SMMU, Coherency and CHI
• LPDDR5 : Strong knowledge and hands-on experience in LPDDR5 protocol knowledge of DDR/DFI, Memory Compliance testing
• UCIe : Expertise and hands-on experience with UCIe verification, including FDI/RDI concepts.
• Network and Memory Encryption : Strong domain expertise in Memory Encryption/Decryption (AES-XTS) and Ethernet MACSec
• Ethernet : Strong Arch knowledge in Ethernet domain including Controller, Serdes for various port modes and speeds
• PCIe/CXL : Strong Architecture domain knowledge in latest generation of PCIE and CXL protocols, PIPE, serdes
• Prior experience and knowledge of APB/AXI/CHI bus protocols, Serial peripherals (eg: I2C, SPI)

FPGA Prototyping (Platform) Lead

· I n this role you will develop FPGA protypes for Tsavorite's Chiplets and SOC using commercially available FPGA prototype platforms/tools

· Experience in handling RTL-to-Bitstream design cycle on million+ gate FPGAs

· Hands-on experience wiwth design partitioning, Verilog coding for FPGA fit.

· Expertise in timing analysis, design optimization for timing convergence and resource utilization

· Familiarity with Intel/Altera Quartus or AMD Vivado design flows

· Expertise in handling standard debugging tools such as ChipScope or custom debug tools

Preferred Experience : Expertise in configuring and bringing up HardIP/embedded ARM Cores.

· FPGA Design experience with any High Speed IO Protocols (PICe, Ethernet,CXL), configuring and bringup of Softcore Processor Microblaze (Xilinx) or Nios (Altera)

Physical Design Verification Engineers

·  Hands-on experience with defining methodology and setting up Physical Verification flows for both Block and SoC-level designs

· Expertise in industry standard tools used for physical verification, such as Mentor Calibre, CalibreDRV, V2LVS, etc.

· Exposure to implementation tools like Innovus/ICC2 is a plus.

Physical Design Engineers

·  Experience in Physical Design implementation (from RTL to GDS) at Block or SoC designs on advanced process nodes

· Expertise and experience with industry-standard CAD tools from Synopsys, Cadence or Siemens.

· Experience in collaborating with RTL design and Flows teams to drive feasibility studies and converge Block/SoC designs to meet target power, frequency, and area targets.Company Descriptio n