Proxelera

Proxelera helps semiconductor teams reduce risk and accelerate silicon delivery with end-to-end product engineering. It delivers ASIC/SoC design, RTL, verification, FPGA prototyping, and embedded…

AI ChipsChip DesignIP DesignNetworking SiliconProduct EngineeringSemiconductorsSilicon ValidationSystem Softwareproxelera.com

Proxelera

Proxelera helps semiconductor teams reduce risk and accelerate silicon delivery with end-to-end product engineering. It delivers ASIC/SoC design, RTL, verification, FPGA prototyping, and embedded…

AI ChipsChip DesignIP DesignNetworking SiliconProduct EngineeringSemiconductorsSilicon ValidationSystem Softwareproxelera.com

HQBengaluru, IN

Team Size124

Open Jobs7

Total Funding-

Latest FundraiseUnknown

Join the Team

Functional Verification Engineer

On-SiteHyderabad, Telangana, IN

On-Site • Hyderabad, Telangana, IN

Startup jobs. A lot of them.

Your next opportunity is in here somewhere. Sign up to explore 70,000+ startups and their open roles. No spam. No gamification. Just jobs.

70,000+

Startups

83,000+

Open Roles

4,300+

New This Week

Machine Learning Engineer

Part-timeRotterdam, NL

Part-time • Rotterdam, NL

Product Designer

InternshipMunich, DE

Internship • Munich, DE

Technical Writer

Part-timeUtrecht, NL

Part-time • Utrecht, NL

Frontend Developer

ContractNovi Sad, RS

Contract • Novi Sad, RS

Mobile Developer

Full-timeBerlin, DE

Full-time • Berlin, DE

Machine Learning Engineer

ContractBerlin, DE

Contract • Berlin, DE

Job Title: Functional Verification Engineer

Location: Hyderabad

Work Mode: Work From Office (WFO)

Role Summary

We are looking for an experienced Functional Verification Engineer with strong hands-on expertise in SystemVerilog/UVM . The ideal candidate will be proactive, self-driven, and capable of independently managing deliverables while working on block-level and IP-level verification.

Key Responsibilities

Develop and maintain block-level testbenches using SystemVerilog/UVM.
Create and execute verification plans (V-Plans) , run regressions, and drive coverage closure .
Work on testbenches with Real Number Modelling (RNM) .
Perform netlist and gate-level simulations (GLS) .

Qualifications & Experience

Education: Bachelor’s degree or higher in Electronics or related field.
Experience: 5–10 years in Functional Verification.

Technical Skills

Strong hands-on coding experience in SystemVerilog/UVM .
Proven experience in block/IP-level verification ; subsystem/SoC-level experience is an added advantage.

Soft Skills

Strong communication skills.
Ability to work independently and meet delivery schedules.

Strict Checklist (Must-Have Requirements)

✔ Pure DV role with expertise in developing TB environments and components

✔ GLS experience: 0-delay and timing simulations

✔ Experience in integrating Real Number Models into the TB and running digital simulations

✔ Strong experience in IP verification coverage closure (100% code + 100% functional coverage)

✔ Typically expected in engineers with 6+ years of DV experience