
Proxelera helps semiconductor teams reduce risk and accelerate silicon delivery with end-to-end product engineering. It delivers ASIC/SoC design, RTL, verification, FPGA prototyping, and embedded software, including IP design and post-silicon validation. The company performs physical design, fab interfacing, and silicon productization, leveraging SystemVerilog, UVM, Python, C/C++, Linux, and Yocto. It supports collaboration with hardware teams and offers outcome-based engagements and royalty-based models, serving global semiconductor customers. With over 190 engineers across Bengaluru and Mysuru and global sales in the USA and Japan, Proxelera scales turnkey chip design projects.

Proxelera helps semiconductor teams reduce risk and accelerate silicon delivery with end-to-end product engineering. It delivers ASIC/SoC design, RTL, verification, FPGA prototyping, and embedded software, including IP design and post-silicon validation. The company performs physical design, fab interfacing, and silicon productization, leveraging SystemVerilog, UVM, Python, C/C++, Linux, and Yocto. It supports collaboration with hardware teams and offers outcome-based engagements and royalty-based models, serving global semiconductor customers. With over 190 engineers across Bengaluru and Mysuru and global sales in the USA and Japan, Proxelera scales turnkey chip design projects.
Job Title: Functional Verification Engineer
Location: Hyderabad
Work Mode: Work From Office (WFO)
Role Summary
We are looking for an experienced Functional Verification Engineer with strong hands-on expertise in . The ideal candidate will be proactive, self-driven, and capable of independently managing deliverables while working on block-level and IP-level verification.
Key Responsibilities
Qualifications & Experience
Technical Skills
Soft Skills
Strict Checklist (Must-Have Requirements)
✔ Pure DV role with expertise in developing TB environments and components
✔ GLS experience: 0-delay and timing simulations
✔ Experience in integrating Real Number Models into the TB and running digital simulations
✔ Strong experience in IP verification coverage closure (100% code + 100% functional coverage)
✔ Typically expected in engineers with 6+ years of DV experience