Smart Silicon

Smart Silicon is a European-based ASIC design and verification partner supporting technology companies globally. With a strong foundation in automotive chip design, they bring a disciplined, rigorous, and safety-critical mindset to demanding applications, while maintaining agility and collaboration. They offer services including RTL Design & Microarchitecture, High-Level Synthesis, Verification Planning & Strategy, Functional & Formal Verification, Real-Number Behavioral Model Development, Model Cross-Verification, and Physical Design Support. They serve industries such as automotive, consumer electronics, industrial applications, IoT, AI accelerators, and RISC-V-based designs. Their business model is based on providing specialized design services, emphasizing precision engineering, agile execution, and on-time, on-budget delivery.

AI AcceleratorsASIC DesignAutomotiveIoTRISC-VRTL DesignSoCVerificationsmart-silicon.net

Smart Silicon

AI AcceleratorsASIC DesignAutomotiveIoTRISC-VRTL DesignSoCVerificationsmart-silicon.net

HQThessaloníki, GR

Team Size12

Open JobsUnknown

Total Funding-

Latest FundraiseUnknown

Join the Team

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Smart Silicon is seeking an enthusiastic Junior or Medior Functional Verification Engineer with a special focus on UVM (Universal Verification Methodology). The successful candidate will be part of our growing verification team, focusing on providing verification services for automotive ASICs of the global leader in automotive electronics.

Responsibilities

● Define and implement verification plans and test plans to ensure the designs meet quality

and performance goals

● Build and maintain UVM-based verification environments.

● Develop test cases based on hardware requirements.

● Proactively collaborate and communicate with technical and project management regarding

verification status, project progress, and issue resolution.

● Provide comprehensive documentation for verification environment and test cases.

Qualifications

Academic Qualifications

● B.Sc/M.Sc. in Computer Science or Electrical Engineering

Verification Technical Skills

● Experience in SystemVerilog.

● Minimum 2 years of experience in ASIC verification

● In-depth knowledge of Verification methodologies (UVM) and functional coverage

● Experience using Verification EDA tools (Xcelium, Vmanager, VCS, Questa)

Other Technical Skills

● Good knowledge of scripting languages (Python, Bash/shell, Perl, Tcl)

● Familiar with version control systems (Git, Helix Perforce)

● Nice to have experience in automotive designs compliant with ISO26262.

● Understanding of digital logic

Soft Skills

● Excellent communication skills.

● Proactive problem solver

● Team Player

● Fluency in English.

Workplace Policy

On-site/Hybrid

On-Site Location

Marousi or Thessaloniki, Greece

Job Posting Available at: https://bit.ly/smart-silicon-fv-engineer