FPGA Design Engineer - AI and HPC Networking | Oriole · Teeming.ai
Oriole
A new company that will revolutionise the performance of AI systems and speed up data centres, whilst dramatically reducing energy consumption for a sustainable future.
A new company that will revolutionise the performance of AI systems and speed up data centres, whilst dramatically reducing energy consumption for a sustainable future.
Product focus: Full-photonic switching and network fabrics for AI/ML and HPC (PRISM, PRISM Ultra)
Total reported recent funding: $22M Series A (after prior £10M seed)
Employee count: ~70
Company Overview
Problem Domain
Data-centre networking for AI/ML and HPC with emphasis on throughput, latency and energy efficiency.
Founded
2023
Industry
Networking / Photonics / AI infrastructure
Tech Stack
Photonic switching
Optical networking
Network fabric design
Funding Track Record
Seed
£10M
Seed round reported with backing from the Clean Growth Fund among others.
Series A- October 2024
$22M
Round reported led by Plural; company noted total raised that year reached $35M.
Investor Signal
“Investors include Plural, UCL Technology Fund, XTX Ventures, Clean Growth Fund and Dorilton Ventures; Innovate UK Investor Partnership participated in prior activity.”
Founders
What we do
Join the Team
FPGA Design Engineer - AI and HPC Networking
HybridLondon Area, GB
Hybrid • London Area, GB
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At Oriole Networks, we are developing disruptive technologies for AI/ML and HPC networking that will revolutionise Data Centers. These technologies will speed up training and inference while dramatically reducing energy consumption for a sustainable future.
We are looking for an experienced FPGA Engineer with passion and experience in prototyping and experiments. The engineer will work iteratively through a series of prototypes to ultimately deliver a production-grade solution. Responsibilities will include microarchitecture definition, implementation, and testing, as well as interfacing with software.
Responsibilities:
Microarchitecture definition in collaboration with the broader team.
Preparing detailed technical documentation and presentations to stakeholders.
RTL Implementation, synthesis, timing closure.
Unit verification planning and simulation testing using SystemVerilog.
Delivering and validating FPGA-based lab setups for customer trials.
Skills & Experience:
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Extensive hands-on industrial experience of FPGA design for network applications at 100Gbps and above.
Experience with high-performance FPGA devices: Xilinx Versal Premium.
Bare metal use of high-speed transceivers such as GTM/GTY.
Experience and good understanding of packet processing and MAC protocol, PTP etc. Experience using PCIe (at least 4th gen) though it is optional.
