We are looking for a highly experienced Digital Front-End Lead with strong expertise in RTL Design and Chip-Level Verification . The ideal candidate will be a hands-on technical leader capable of driving SoC/MCU architecture, RTL quality, and end-to-end verification closure while mentoring a high-performing team.

Experience with ARM-based MCU products is highly preferred.

Key Responsibilities

1. Chip-Level & SoC Verification

• Define and own chip-level verification strategy and plan
• Extract use cases and derive verification scenarios
• Develop dynamic & static verification environments
• Drive coverage closure and Gate-Level Simulation (GLS) with back-annotated delays
• Ensure robust verification sign-off

2. RTL Design & Quality

• Hands-on RTL coding (Verilog / SystemVerilog)
• Define RTL coding standards and quality metrics
• Perform RTL reviews and lint/quality checks using EDA tools
• Collaborate on micro-architecture definition

3. Synthesis & Timing

• Create and validate SDC constraints
• Run synthesis trials and review STA reports
• Coordinate with backend for timing closure

4. Leadership & Collaboration

• Lead and mentor DFE/Verification engineers
• Plan milestones and track execution
• Work closely with Backend, Analog, and Test teams
• Support silicon bring-up and production validation

Required Experience

• 8–15 years in ASIC / SoC Digital Front-End
• Strong expertise in RTL Design and Chip-Level Verification
• Experience with MCU/ARM-based SoCs
• Solid understanding of ASIC design flow (RTL → Synthesis → STA → GLS → Tape-out)
• Prior team leadership experience

Location: Bangalore