of physical design stages, ensuring high-quality tape-out with optimized performance, power, and area (PPA).

Key Responsibilities

• Own and execute the complete RTL-to-GDSII physical design flow.
• Perform floor planning, placement, clock tree synthesis (CTS), routing, and timing closure.
• Conduct power optimization, congestion analysis, and ECO (Engineering Change Order) implementation.

Drive signoff activities, including:

• Static Timing Analysis (STA)
• IR drop and Electromigration (IR/EM) analysis
• Physical verification (DRC/LVS)
• Work closely with front-end design, DFT, and packaging teams for seamless design integration
• Debug and resolve timing, signal integrity, and physical design
• issues
• Ensure design meets PPA targets (Performance, Power, Area)
• Support tape-out and post-silicon activities as required

Education:

Bachelor´s or Master´s degree in in

Electronics / Electrical / VLSI Engineering.

Experience:

• Experience working on full-chip or block- level physical design.
• Prior experience in high-performance or low-power designs is a plus.

Technical Skills:

Strong hands-on experience with:

• Synopsys ICC2 or Cadence Innovus
• Ansys tools (for power integrity / thermal analysis)

Expertise in Static Timing Analysis (STA) using Prime Time

Good understanding of:

• Low power design techniques
• Signal integrity and noise analysis
• Physical verification (DRC/LVS)

Familiarity with scripting languages such as Tcl/Python is an added advantage