In this role, you will be building the digital part of SEMRON’s future chip generations. You will design, verify, and optimize digital designs to meet our ambitious performance targets.

Responsibilities

• Design the digital part of SEMRON’s AI accelerator
• Contribute to system architecture exploration efforts
• Work closely with the analog and software team to exchange requirements and implement them
• Conduct power, performance, and timing analysis
• Develop timing constraints

Qualifications

• In-depth knowledge in RTL design
• Experience with RTL simulation tools
• A good understanding of digital design trade-offs
• Basic knowledge of scripting (e.g., Tcl, Python) and systems programming (e.g., C, C++)
• Familiarity with low power design techniques

Helpful but Not Required

• Experience with the Chisel HDL
• Experience in verification
• Experience in mixed signal simulation
• Experience with RISC-V