🚀 We’re Hiring: Digital Place & Route Engineer
Location:
Hybrid
Experience:
0–5 Years
Company:
Mabrains
About Mabrains
Mabrains is an AI-driven technology company transforming chip design through intelligent automation and next-generation EDA workflows. We focus on building scalable, efficient design systems that combine proven semiconductor design methodologies with AI-powered innovation.
Role Overview
We are looking for a
Digital Place & Route Engineer
with a
strong preference for mid-level experience
to join our engineering team. The role focuses on full RTL-to-GDSII implementation targeting
22nm CMOS technology
, using industry-standard Synopsys tools.
Key Responsibilities
- Perform
digital place and route (PnR)
using
Synopsys ICC2
- Implement and optimize physical design flows targeting
22nm CMOS nodes
- Run
Design Compiler
synthesis and support RTL-to-GDS handoff
Required Qualifications
- 0–5 years of experience in
digital physical design
, with
mid-level candidates strongly preferred
- Hands-on experience with
Synopsys ICC2
- Solid experience using
Synopsys Design Compiler
- Strong understanding of timing analysis, clocking, and digital design fundamentals
- Familiarity with ASIC implementation flows from synthesis through sign-off
- Experience working in
Preferred Qualifications (Nice to Have)
- Prior hands-on experience with
22nm CMOS technologies
- Experience with STA and MCMM sign-off flows
- Scripting skills in
Tcl
,
Python
, or
Shell
- Exposure to sign-off and physical verification tools (e.g., PrimeTime, DRC/LVS)
- Interest in automation, AI-assisted design, or open-source EDA tools
What We Offer
- Opportunity to work on
production-grade silicon designs
- Exposure to
AI-driven EDA and design automation
- A collaborative, engineering-focused culture
- Competitive compensation aligned with experience
- Flexible work environment
How to Apply
If you are a motivated physical design engineer looking to grow in a high-impact role, we’d love to hear from you.
https://careers.mabrains.com/
