Qualification/Experience/Skills Required
- Strong expertise in Design-for-Test (DFT) methodologies, including MBIST, Scan, and Boundary Scan.
- 5+ years of hands-on experience across the complete DFT flow: insertion, pattern generation, simulation (with and without SDF), and DvD checks for DFT patterns.
- Solid understanding of Static Timing Analysis (STA) concepts.
- Proven experience in DFT SDC development and timing closure.
- Direct exposure to silicon bring-up support and debug.
- Experience with 3D IC design and integration is a significant advantage.
- Strong analytical, problem-solving, and debug skills.
- Effective time and risk management abilities.
- Excellent communication and collaboration skills, with the ability to work effectively across functions.
Roles & Responsibilities
- Collaborate with the DFT Architect to define and deploy the DFT micro-architecture for each project.
- Lead and mentor the DFT team, ensuring timely and accurate implementation of all required features.
- Work closely with other functions: customer, design team, PI and PD team during the execution.
- Work with the product, test teams to ensure successful silicon bring-up
- Drive continuous improvement by optimizing DFT flows to be timing-aware, power-aware, and efficiency-aware.
- Provide technical guidance and support to team members, helping resolve complex design or debug challenges.
- Contribute to the adoption and development of next-generation DFT technologies.
Educational Qualification
- Bachelor’s degree (or equivalent experience) or above.
