Key Responsibilities

Technical Leadership

• Own and drive the end-to-end DFT architecture and implementation for SoC and IP designs.
• Define and review DFT methodologies, including Scan Insertion, ATPG, MBIST , and test coverage closure.
• Lead scan architecture definition , including compression, low-power DFT, and test access mechanisms.
• Drive MBIST architecture, controller integration, and memory test coverage across multiple memory types.
• Ensure high fault coverage , optimal test time, and manufacturability targets.

Execution & Delivery

• Oversee DFT implementation, verification, and sign-off across project milestones.
• Review and sign off on ATPG patterns, fault models, and test reports .
• Collaborate closely with RTL, Physical Design, STA, Verification, and Silicon teams to resolve DFT-related issues.
• Support post-silicon debug, yield improvement, and production test correlation .

People & Stakeholder Management

• Lead, mentor, and grow a team of DFT engineers .
• Plan resource allocation, training, and performance management.
• Act as the primary DFT interface with internal stakeholders and external partners/foundries.
• Drive continuous improvement in DFT flows, automation, and best practices .

Required Skills & Experience

Technical Expertise

• 12–18 years of hands-on experience in DFT for ASIC/SoC designs .
• Strong expertise in:
• Scan Insertion (full scan, partial scan, scan compression)
• ATPG (stuck-at, transition, path delay, at-speed testing)
• MBIST (architecture, implementation, and coverage closure)
• Solid understanding of DFT-aware RTL design and testability guidelines .
• Experience with low-power DFT , test time optimization, and yield enhancement techniques.
• Leadership & Communication
• Proven experience managing and mentoring technical teams.
• Strong problem-solving, analytical, and decision-making skills.
• Excellent communication skills to work across cross-functional and global teams.

Education

• Bachelor’s or Master’s degree in Electronics / Electrical Engineering or a related field.

Nice to Have

• Experience with automotive, safety-critical, or high-reliability designs .
• Exposure to production test, ATE correlation, and yield ramp-up .
• Experience driving DFT methodology standardization across multiple projects.

About Us:

Silicon Patterns is a specialized engineering services company with deep expertise in pre-silicon and post-silicon design and verification. We deliver end-to-end semiconductor and embedded system solutions covering RTL Design, SystemC Modeling, Emulation, Design Verification (DV), Physical Design (PD), Design for Testability (DFT), and Pre- & Post-silicon Validation — helping clients achieve faster, more reliable product development. Headquartered in Hyderabad, with offices in Bangalore and Raipur, and supported by our skilled engineering teams in Malaysia, we serve global clients through flexible engagement models like Time & Materials (T&M), Offshore Development Centers (ODC), Subcontracting, and Build-Operate-Transfer (BOT). Our expertise spans VLSI and Embedded Systems, with a strong focus on Wireless, IoT, and Automotive domains. We also work on advanced technologies including HBM3/3E workloads, AI/ML, GenAI/LLMs, and edge computing. At Silicon Patterns, we’re committed not only to technical excellence but also to maintaining a strong work-life balance for our teams because great engineering starts with well-supported people.

Website

https://www.siliconpatterns.com