Key Responsibilities

Architectural Ownership

• Define and drive the overall DFT architecture for large-scale SoCs, including scan, BIST (LBIST/MBIST), boundary scan, compression, and hierarchical DFT methodologies.
• Architect scalable and reusable DFT infrastructure compliant with design, technology, and test requirements.
• Review RTL, synthesis, physical, and test constraints to ensure robust DFT integration.

DFT Strategy & Execution

• Own end-to-end DFT flow: planning, insertion, verification, pattern generation, silicon bring-up, and production test.
• Lead ATPG flow , including stuck-at, transition, path delay, and cell-aware testing.
• Define and implement MBIST architectures , memory test algorithms, redundancy strategies, and repair flows.
• Provide guidance on JTAG/IEEE 1149.x , boundary scan, TAP controllers, and test access mechanisms.

Team Leadership & Collaboration

• Lead and mentor a team of DFT engineers, providing technical direction, reviews, and skills development.
• Collaborate with cross-functional teams (RTL, PD, verification, silicon validation, product engineering, test engineering).
• Drive design reviews, signoffs, and best-practice adoption across business units.

Silicon Bring-Up & Test Interface

• Support silicon debug, yield improvement, failure analysis, and test program optimization.
• Interface with ATE/test teams to ensure seamless pattern bring-up and debug on testers.

Innovation & Process Improvement

• Evaluate new DFT tooling, automation, and methodologies to improve test coverage, cost, and time to market.
• Establish DFT guidelines, documentation, and reusable frameworks for global teams.

Required Skills & Expertise

Core Technical Expertise

• Strong proficiency in DFT architecture for complex SoCs.
• Deep hands-on experience in:
• Scan insertion & compression techniques
• ATPG (Synopsys TetraMAX/TestMAX, Mentor FastScan, etc.)
• MBIST (Synopsys DFTMAX, Cadence Modus, Tessent MBIST)
• Boundary Scan / JTAG , 1149.1/6/7
• LBIST , MISR, PRPG, test points
• Hierarchical DFT , multi-core SoCs
• Strong understanding of RTL design, synthesis, STA, PnR, and low-power architectures .

Tools Expertise

• Synopsys DFTMAX/SpyGlass DFT/TestMAX
• Siemens Tessent (Scan, ATPG, MBIST, LBIST)
• Cadence Modus
• Debug tools: Verdi, VCS, Questa, DFT synthesis tools
• ATPG debug & tester bring-up tools

Leadership Competencies

• Proven experience leading and architecting DFT solutions across multiple tape-outs.
• Ability to guide teams through complex technical challenges.
• Strong communication, stakeholder management, and problem-solving skills.

Education

• Bachelor’s or Master’s degree in Electronics, Electrical, or Computer Engineering , or related field.

Preferred Qualifications

• Experience with advanced technology nodes (7nm, 5nm, below) .
• Exposure to Automotive/Functional Safety (ISO 26262) DFT requirements.
• Experience in test cost optimization and yield-enhancement strategies.

Why Join Us?

• Opportunity to architect DFT for cutting-edge silicon used across global markets.
• Work with world-class engineering teams in a fast-paced innovation ecosystem in Bengaluru.
• Leadership role with high visibility and technical ownership.

About Us:

Silicon Patterns is a specialized engineering services company with deep expertise in pre-silicon and post-silicon design and verification. We deliver end-to-end semiconductor and embedded system solutions covering RTL Design, SystemC Modeling, Emulation, Design Verification (DV), Physical Design (PD), Design for Testability (DFT), and Pre- & Post-silicon Validation — helping clients achieve faster, more reliable product development. Headquartered in Hyderabad, with offices in Bangalore and Raipur, and supported by our skilled engineering teams in Malaysia, we serve global clients through flexible engagement models like Time & Materials (T&M), Offshore Development Centers (ODC), Subcontracting, and Build-Operate-Transfer (BOT). Our expertise spans VLSI and Embedded Systems, with a strong focus on Wireless, IoT, and Automotive domains. We also work on advanced technologies including HBM3/3E workloads, AI/ML, GenAI/LLMs, and edge computing. At Silicon Patterns, we’re committed not only to technical excellence but also to maintaining a strong work-life balance for our teams because great engineering starts with well-supported people.

Website

https://www.siliconpatterns.com