-Run atpg, analyze coverage, use VCS and Questa to simulate

at unit & sdf.

-Perform test insertion for embedded block in SoC.

-Performing general DFT work on SoC.

-Using Cadence tools(modus) to insert/verify DFT logic.

Some tasks in include, running ATPG to verify DFT

implementation is working at block and chip level, perform fault

coverage analysis, root cause low coverage issues, simulate

ATPG and MBIST to verify DFT structure and patterns, work

with PD to close timing on post-layout netlists, create silicon

bring up plan/strategy.

Used Siemens DFT tools to perform test insertion for

embedded block in SoC.

Used Makefile, TCL, Python to perform DFT insertion

Automation.

Contact:

Supriya Sharma

Supriya@mulyatech.com