• Develop testbench components such as test, sequence libraries, bfm and monitor by using object oriented programming verification techniques following UVM methodology
• Automate validation environment to improve activities such as test writing, regression running or coverage collection
• Define detailed testplan from specification by working with architects and design engineers
• Write and debug tests in UVM/C++
• Incorporate function/code-coverage, assertions, cover-groups etc to achieve 100% verification completeness prior to tapeout
• Experience in PCIe/Ethernet/DDR/USB will be a plus
• Train up juniors in the validation team

Qualifications

• Knowledge in C, Python, shell scripting
• OVM/UVM validation methodology
• Verilog/System Verilog
• Great interpersonal and communication skills
• Minimum 6 years hands-on experience
• Team player, critical thinker and problem solving skills