
SkyeChip helps companies develop custom silicon for AI and high-performance computing by providing end-to-end chip design and IP. The company delivers architecture and micro-architecture,…

SkyeChip helps companies develop custom silicon for AI and high-performance computing by providing end-to-end chip design and IP. The company delivers architecture and micro-architecture,…
Job title: Junior/Senior/Staff Design Verification Engineer
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Location: KL/Penang (on-site)
Job Type: Full-time Malaysians only and/or have permit to work in Malaysia
We are growing and looking for self-motivated, multi-tasker, and demonstrated team-player. This position will be responsible for RTL verification, debug, functional coverage tasks, testplan development, and new verification methodology.
Key Responsibilities
-Develop and maintain UVM-based verification environments for IP designs.
-Create detailed test plans based on design specifications, architectural documents, and use-case scenarios.
-Implement constrained-random testbenches, scoreboards, and monitors to validate functional behavior.
-Perform coverage-driven verification, including:
o Functional coverage (covergroups, coverpoints)
o Code coverage (statement, branch, toggle)
o Assertion coverage (SystemVerilog assertions)
-Drive coverage closure by identifying gaps and enhancing test scenarios.
-Execute gate-level simulations to validate timing, reset sequences, and power-up behavior post-synthesis.
-Apply Formal Property Verification (FPV) to prove critical design properties and uncover corner-case bugs.
-Debug simulation failures and collaborate with RTL designers to resolve issues efficiently.
-Document verification results, coverage metrics, and regression summaries for traceability and quality assurance.
Qualifications
-Bachelor's or Master's degree in Electrical Engineering or related field
-RTL Verification and Debugging skills
-Validation and Functional Verification expertise
-Knowledge of pre-silicon verification methodologies
-Strong analytical and problem-solving skills
-Experienced with industry-standard EDA tools
-Certifications in validation or verification processes are a plus
-Experienced on UVM testbench development and system verilog
*Added advantages:
-Capable of developing BFM will be advantage
-Have worked or working on IP such as PCle, UCle, Ethernet, AXI