Position: Design Verification Engineer (IP / SoC / Low-Power SoC)

Experience: 5 to 10 years

Location: Bengaluru

Job Description:

We are looking for experienced Design Verification Engineers to work on complex IPs, SoCs, and low-power SoC designs. The role involves hands-on verification, testbench development, coverage closure, and debugging of advanced semiconductor designs.

Key Responsibilities:

• Perform functional verification of IPs, SoCs, or sub-systems using SystemVerilog and UVM
• Develop verification testbenches from scratch or build major TB components such as drivers, sequencers, monitors, agents, scoreboards, and checkers
• Create detailed testplans from design specifications and ensure complete feature coverage
• Execute functional and code coverage, identify coverage gaps, and write directed and constrained-random tests
• Debug complex issues using waveform analysis and simulation tools
• Work closely with design, architecture, and validation teams to resolve verification issues

Required Skills & Experience:

• 5–10 years of hands-on Design Verification experience in IP-level or SoC-level verification
• Strong experience in SystemVerilog and UVM methodology
• Experience verifying industry-standard protocols such as PCIe, AXI, CHI, or UCIe
• Excellent debugging skills using tools like Verdi, Verisium, or SimVision
• Experience in coverage-driven verification and closure