We have a very exciting opportunity for Digital Verification Engineers in Cambridge .

Our client is growing their DV team , making this a great time to join and have real influence from the ground up.

This is your chance to help shape verification strategy and standards as the team scales.

The work focuses on production-ready, open-source silicon , including Ibex CPU and OpenTitan , developed with world-leading partners such as Google .

You will work on industrial-strength verification across block and system level designs, including RISC-V cores, cryptographic IP, and key peripherals .

Responsibilities

• Design, implement, and debug SystemVerilog/UVM testbenches
• Develop verification plans, tests, and coverage
• Review open-source contributions and debug regressions
• Contribute to test and CI infrastructure
• Collaborate with partners to support successful tapeouts

Requirements

Essential

• 5+ years’ industry experience in design verification
• Strong SystemVerilog and UVM experience
• Full verification lifecycle experience through tapeout
• C and/or Python for tests and automation
• Git/GitHub and collaborative team experience

Desirable

• Formal verification (e.g. Jasper)
• RISC-V or ISA experience
• Security verification knowledge
• Silicon bring-up or post-silicon debug
• Technical leadership experience

Benefits

• 25 days annual leave + 8 bank holidays
• Employer pension contribution
• Private medical insurance, income protection, critical illness and life cover
• Opportunities to attend industry conferences and training

If you could be interested for this position, please get in touch and share your CV with me tee@microtech-global.com