You will be responsible for defining and executing verification strategies, leading junior engineers, and ensuring first-pass silicon success.

Key Responsibilities

Verification Strategy & Planning

• Develop verification plans, test strategies, and coverage models for IP/Subsystem/SoC-level verification.
• Drive UVM-based verification methodology and maintain reusable environments.
• Analyze design specifications, micro-architecture documents, and identify corner cases.

Testbench & UVM Environment Development

• Architect and build complex UVM components: drivers, monitors, scoreboards, sequencers, virtual sequences.
• Develop constraint-random and directed tests to validate functionality and robustness.
• Create assertions (SVA) and checkers for functional correctness.

Simulation, Debugging & Coverage

• Execute simulations using industry-standard simulators (Questa, VCS, Xcelium).
• Debug complex failures using waveform viewers and logs.
• Perform functional, code, and assertion coverage analysis and drive coverage closure.

Collaboration & Leadership

• Work closely with RTL designers, architects, and firmware teams to resolve issues.
• Provide technical guidance and mentoring to junior DV engineers.
• Participate in design and verification reviews; contribute to methodology enhancements.

Required Skills & Experience

• 8+ years of experience in ASIC/SOC/IP Design Verification.
• Deep expertise in SystemVerilog , UVM , and SV Assertions .
• Strong understanding of digital design fundamentals, SoC architecture, and verification methodologies.
• Hands-on experience in constrained-random testing , coverage-driven verification , and scoreboard-based checking .
• Proficient with industry-standard simulation tools (VCS/Questa/Xcelium).
• Experience verifying protocols such as AMBA (AXI, AHB, APB) , PCIe, DDR, USB, or similar.
• Strong debug skills using waveform tools (SimVision, DVE, Verdi).
• Excellent documentation, communication, and problem-solving abilities.