Company Description

Chiplogic Technologies, established in 2018, is a trusted IP and Product Engineering Services company specializing in Semiconductor, Systems, IoT, and AI/ML domains. With expertise in delivering high-quality and reliable solutions, Chiplogic offers ODC and full turnkey semiconductor design and system solutions, from concept to silicon. The company also develops IoT solutions and advanced services in the AI/ML domain, leveraging its proprietary VISARD™ (Video Synthesis And Real-time Dynamics) framework.

Job Overview

We are looking for a highly experienced Senior Design Verification Engineer to lead verification activities for complex SoC/IP designs. The ideal candidate must have strong hands-on expertise in SystemVerilog, UVM methodology, verification planning, debugging, coverage closure, and collaboration across multi-disciplinary teams.

You will be responsible for defining and executing verification strategies, leading junior engineers, and ensuring first-pass silicon success.

Key Responsibilities

Verification Strategy & Planning

• Develop verification plans, test strategies, and coverage models for IP/Subsystem/SoC-level verification.
• Drive UVM-based verification methodology and maintain reusable environments.
• Analyze design specifications, micro-architecture documents, and identify corner cases.

Testbench & UVM Environment Development

• Architect and build complex UVM components: drivers, monitors, scoreboards, sequencers, virtual sequences.
• Develop constraint-random and directed tests to validate functionality and robustness.
• Create assertions (SVA) and checkers for functional correctness.

Simulation, Debugging & Coverage

• Execute simulations using industry-standard simulators (Questa, VCS, Xcelium).
• Debug complex failures using waveform viewers and logs.
• Perform functional, code, and assertion coverage analysis and drive coverage closure.

Collaboration & Leadership

• Work closely with RTL designers, architects, and firmware teams to resolve issues.
• Provide technical guidance and mentoring to junior DV engineers.
• Participate in design and verification reviews; contribute to methodology enhancements.

Required Skills & Experience