Standard Cell Design Engineer | Axion | Pangyo Techno Valley
Axion
is a pioneering company developing
AI-powered semiconductor automation and optimization solutions
. Our mission is to revolutionize the semiconductor design process and drive innovation across industries through advanced AI-driven design optimization software.
We’re looking for
passionate and creative engineers
to join us in shaping the future of semiconductor design.
Position
Standard Cell Library Engineer
Responsibilities
- Design and verify
Standard Cell schematic and layout
- Perform
Standard Cell Library characterization
Qualifications
- Bachelor’s degree or higher in
Electrical, Electronics, or Computer Engineering
(or related field)
- Minimum
2 years of relevant experience
in semiconductor design
Preferred Qualifications
- Experience with
RTL-to-GDS
flow
- Hands-on experience in
ASIC back-end (Place & Route)
- Familiarity with
EDA tools
(Synopsys, Cadence, Siemens EDA, etc.)
- Strong scripting skills in
Python, Tcl, or Perl
- Experience at
fabless or foundry companies
Work Conditions
- Location:
Pangyo Techno Valley (221 Pangyoyeok-ro, Seongnam, Korea)
- Employment Type:
Full-time (3-month probation)
- Compensation:
Negotiable, based on experience and interview results
Application Process
- Required Documents:
Resume & Academic Transcript (mandatory), Career Statement (if applicable)
- How to Apply:
Submit via
Saramin
- Application Period:
Open until position is filled
Recruitment Steps
- Document Screening
- 1st Interview (Technical Team)
- 2nd Interview (Executive Panel)
- Final Offer
Contact
For inquiries, visit www.axion-technologies.com →
Contact Us
page.
📢
Join Axion and help us shape the future of semiconductor innovation!
⚠️ Please note that any false information in your application may result in the withdrawal of an employment offer.
