We build GPU accelerated tools for chip designers. Our Electronic Design Automation (EDA) tools offer 1000x runtime improvements without degrading the quality of the output, thus achieving faster…
We build GPU accelerated tools for chip designers. Our Electronic Design Automation (EDA) tools offer 1000x runtime improvements without degrading the quality of the output, thus achieving faster…
We are developing the next generation of chip design automation tools with a focus on performance, scalability and productivity. We envision a future where hardware engineers benefit from advances in AI and believe the first place to start is with advanced optimization tools.
We’re looking for engineers who think in terms of intermediate representations and passes — people who can design the data models that physical-design tools run on, not just use them. You should be able to move seamlessly between high-level IR design and low-level performance work, building the infrastructure that lets placement, routing, and timing engines operate at massive scale.
At Partcl, we’re not here to play it safe - we’re here to win. We want people who wake up every day wanting to win too. If you are interested in solving massive-scale problems in physical AI, come join us.
What you will do:
Requirements:
Strong background in compilers or IR design (LLVM, MLIR, TVM, CIRCT, or equivalent experience)
Deep familiarity with chip backend concepts: floorplanning, placement, routing, CTS, extraction
Nice to Have:
Experience with CIRCT/MLIR or custom EDA IRs
Prior work on static analysis, transformation passes, or compiler runtimes
Knowledge of timing models (CCS/LVF) and constraint propagation
Experience with columnar or in-memory formats (Apache Arrow, Parquet, custom SOA layouts)
Parallel compiler / GPU acceleration experience
Prior ownership of a large-scale EDA database (OpenDB, OA, Innovus/Milkyway internals, etc.)
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Design the core intermediate representations that physical-design tools use to reason about chips
Build compiler-like pipelines that lower, normalize, and transform design data across stages (netlist → floorplan → PnR → sign-off)
Architect the physical-design data model as a first-class IR, not just a storage format
Create high-performance loaders, serializers, and transformation passes for LEF/DEF, Liberty, SPEF, GDS
Develop APIs that make analysis and optimization passes fast to write and reason about
Own correctness invariants: name resolution, scoping, units, coordinate systems, legalizations, constraints
Optimize for query latency, cache locality, memory layout, and parallel traversal
Build validation and rewriting passes that catch inconsistencies and automatically repair design data
Work directly with PnR, STA, and optimization engineers to co-design new IR features and passes
Treat the database as a compiler backend, not a dumping ground
Fluency with physical-design file formats: LEF/DEF, Liberty, SDC, SPEF, GDS
Proficiency in Rust for low-level systems work; Python for tooling and pipelines
Experience designing data structures for large graphs / sparse relations / geometric data
Understanding of incremental computation, dependency tracking, and versioning of IR states
Ability to reason about correctness, determinism, and reproducibility in complex toolchains
Comfortable digging into massive designs and fixing pathological corner cases
