
Avicena is a privately held company headquartered in Sunnyvale, California, with a development center in Edinburgh, Scotland, developing microLED-based ultra-low power, high bandwidth interconnects for chip-to-chip communications. Their technology targets High-Performance Computing (HPC), AI/ML, cloud computing, and other industries requiring low power interconnects such as camera sensors, autonomous vehicles, and aerospace. Avicena's LightBundle™ technology offers advanced chip-to-chip and chip-to-memory interconnects with high temperature operation up to 400ºC and is recognized for its innovation with over 100 patents. The company collaborates with major semiconductor manufacturers like TSMC and is positioned to address the energy efficiency bottleneck in next-generation computing architectures, aiming to reduce the environmental impact of data centers and computing systems.

Avicena is a privately held company headquartered in Sunnyvale, California, with a development center in Edinburgh, Scotland, developing microLED-based ultra-low power, high bandwidth interconnects for chip-to-chip communications. Their technology targets High-Performance Computing (HPC), AI/ML, cloud computing, and other industries requiring low power interconnects such as camera sensors, autonomous vehicles, and aerospace. Avicena's LightBundle™ technology offers advanced chip-to-chip and chip-to-memory interconnects with high temperature operation up to 400ºC and is recognized for its innovation with over 100 patents. The company collaborates with major semiconductor manufacturers like TSMC and is positioned to address the energy efficiency bottleneck in next-generation computing architectures, aiming to reduce the environmental impact of data centers and computing systems.
Avicena is a privately held company developing microLED based ultra-low power high bandwidth interconnects for chip-to-chip communications. This technology will revolutionize High-Performance (HPC) and Cloud computing, as well as other industries where low power interconnects are critical like camera sensors, autonomous vehicles, and aerospace. Avicena is headquartered in Sunnyvale, California with a development center in Edinburgh, Scotland. The company was founded in 2019 by leading technologists from the optical networking industry with a track record of delivering breakthrough products. (www.avicena.tech)
About The Role Avicena is seeking a talented and detail-oriented ASIC Design Verification (DV) Engineer to join our chip design team. You'll play a crucial role in ensuring the functional correctness, performance, and robustness of our high-speed, low-power digital integrated circuits (ICs) for groundbreaking silicon photonics and optical interconnect solutions. This position requires strong expertise in verification methodology and a commitment to quality.
Responsibilities
Qualifications
Required:
Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
Experience: 3+ years of professional experience in ASIC/SoC design verification.
UVM Expertise: Strong proficiency and hands-on experience in building and deploying reusable verification environments using SystemVerilog and UVM.
Verification Languages: Expertise in SystemVerilog, and knowledge of scripting languages like Python or Perl.
Tool Proficiency: Experience with industry-standard EDA simulation and debug tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa).
Coverage Driven Methodology: Solid understanding of constrained-random verification and functional/code coverage analysis.
Debugging Skills: Excellent analytical and problem-solving skills with a proven ability to debug complex digital logic and verification environments.
Preferred (Nice to Have):
Experience verifying high-speed interfaces, SerDes, or communication protocols like Ethernet and PCIe.
Exposure to forward error correction (FEC), scrambling, and other digital data communication techniques.
Knowledge of formal verification tools (e.g., Synopsys VC Formal, Cadence JasperGold).
Familiarity with low-power verification techniques.
Experience with hardware description languages (HDL) like Verilog/SystemVerilog for basic design understanding.
Exposure to physical layer (PHY) or mixed-signal verification concepts.