
Proxelera helps semiconductor teams reduce risk and accelerate silicon delivery with end-to-end product engineering. It delivers ASIC/SoC design, RTL, verification, FPGA prototyping, and embedded…

Proxelera helps semiconductor teams reduce risk and accelerate silicon delivery with end-to-end product engineering. It delivers ASIC/SoC design, RTL, verification, FPGA prototyping, and embedded…
We’re hiring an ASIC Design Engineer who can take full ownership of complex SoC and subsystem RTL from concept to silicon. You’ll define micro-architecture, craft clean Verilog RTL, drive synthesis, timing closure, and work hand-in-hand with integration and backend teams to land a production-ready design. Expect deep involvement across reviews, debug cycles, emulation, and bring-up.
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You should bring 8–15 years of solid ASIC RTL experience, strong micro-architecture thinking, and hands-on skills across synthesis, timing, and SoC integration. Expertise with high-speed protocols (PCIe, DDR/LPDDR, USB, Ethernet, SPI/I3C/I2C, etc.), RTL assertions/coverage, and cross-team collaboration is key. Comfort with scripting (Perl/Python) and FPGA-based emulation platforms like HAPS or Veloce is highly valued.
If you’re looking for meaningful ownership and a chance to influence real silicon, this is the role to consider.
Best,
Karthik Kumar
karthik.adasu@Proxelera.com