Location:
Kraków or Gliwice (Poland) | Remote/Hybrid possible
At
Vtool
, we help semiconductor companies accelerate ASIC development through a combination of
expert design services
and
innovative EDA technology
(including our AI-powered analytics & debug platform,
Cogita-PRO
).
We are expanding our design team in Poland and looking for experienced, self-driven engineers who enjoy working across
multiple projects, customers, and technology stacks
.
What you’ll do
Own
micro-architecture and RTL design
of digital blocks/subsystems (from spec to delivery).
Translate ambiguous requirements into clear design decisions, docs, and implementation.
- Integrate and customize
3rd-party and in-house IP
, collaborate on SoC/subsystem integration.
- Work closely with verification, physical design, and software teams to drive quality and schedule.
- Support debug, performance/power improvements, and design reviews across projects.
- Contribute to reusable methodologies, automation, and engineering best practices.
What we’re looking for
Nice to have (optional)
- FPGA prototyping / emulation experience (main focus remains ASIC).
- Experience with lint/CDC, synthesis constraints, timing concepts, or collaboration through timing closure.
- Scripting/programming for productivity (Python, Tcl, C/C++).
- Exposure to formal verification, security blocks, networking datapaths, compute accelerators, or safety-critical flows (project-dependent).
Why Vtool
Broad technical exposure: different products, standards, and design styles—ideal if you enjoy
variety and ownership
.
- Growth path toward
technical leadership / architecture
, plus strong peer environment and knowledge sharing.
- Work with an organization focused on accelerating ASIC outcomes for customers worldwide.
Interested?
Send your CV / LinkedIn profile (and a short note: your strongest domains + what you want to build next) to:
rekrutacja@thevtool.com
****
Keywords/hashtags:
#ASIC #RTL #DigitalDesign #SystemVerilog #SoC #VLSI #EDA #Semiconductor #Krakow #Gliwice #Remote
