Empower Semiconductor

Empower Semiconductor provides integrated voltage regulator technology that reduces power, size, and energy cost for modern computing systems. The company develops a patent-pending power management…

AI HPC Power SolutionsChiplet Power SolutionsHigh Bandwidth Power SolutionsHigh Power Density SolutionsIntegrated Voltage Regulators (IVRs)Kilowatt-Class Processor Power DeliveryPower IntegritySilicon CapacitorsVertical Power Deliveryempowersemi.com

Empower Semiconductor

HQMilpitas, US

Team Size69

Open Jobs2

Total Funding$215M

Latest Fundraise9 months ago

Join the Team

Analog / Mixed Signal Layout Engineer

On-SiteMünchen, DE

On-Site • München, DE

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Title: Analog/Mixed-Signal Layout Engineer

Location: Munich (Germany)

Job Type: Full-time

About the company

Empower Semiconductor, based in Silicon Valley, powers the AI revolution with its FinFast™ technology by reducing the energy footprint and total cost of ownership of data centres. Its transformational integrated voltage regulators deliver on-demand scalable power with the speed, precision and signal integrity required by AI processors. Empower’s power-management architecture shrinks solution footprint, height and component count, achieving vertical power delivery with unprecedented power density and efficiency. Learn more at www.empowersemi.com and follow us on LinkedIn.

Role Overview

To expand the team in Munich we are seeking an experienced Analog/Mixed-Signal layout Engineer to contribute to the development of high-performance power management ICs in advanced CMOS nodes. In this role, you will collaborate closely with circuit designers to deliver high-density, ultra efficient layout implementations that meet aggressive performance and size targets.

The ideal candidate has 5-10 years of hands-on experience, deep expertise in custom analog layout, and thrives in a startup-like, high-accountability culture.

Key Responsibilities

Execute full-custom layout of analog/mixed-signal building blocks including LDOs, bandgaps, opamps, comparators, and switching regulators
Floorplan and implement top-level analog/mixed-signal blocks with attention to matching, shielding, routing symmetry, and parasitic
Perform physical verification: DRC, LVS, ERC using industry standard tools
Collaborate with designers to iterate and optimize layouts based on circuit sensitivities and extracted simulation results
Ensure reliability and manufacturability through proper layout practices

Qualifications:

BS or MS in Electrical Engineering with 5+ years’ experience in Power IC design
Expert-level proficiency with Cadence Virtuoso and verification tools
Strong understanding of analog layout techniques: device matching, noise isolation, current density, and thermal awareness
Strong sense of ownership/accountability; able to work independently and collaboratively in a team environment.
Experience with FinFet layout is desirable
Good communication skills (verbal, written)