
Proxelera helps semiconductor teams reduce risk and accelerate silicon delivery with end-to-end product engineering. It delivers ASIC/SoC design, RTL, verification, FPGA prototyping, and embedded…

Proxelera helps semiconductor teams reduce risk and accelerate silicon delivery with end-to-end product engineering. It delivers ASIC/SoC design, RTL, verification, FPGA prototyping, and embedded…
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If custom analog layout is your playground and tape-outs are your milestones, this one’s built for you.
Role Scope
Lead end to-end custom layout for Analog/Mixed-Signal IPs and custom-digital blocks in a full SoC flow
Deliver PV-clean layouts with zero surprises at DRC/LVS
Drive floorplanning, routing, matching, parasitic control, signal integrity, power distribution, and area optimization
Review layouts with Analog Design teams and align on trade-offs
Mentor junior layout engineers and set quality benchmarks
Plan schedules and execution strategy in close sync with design teams
Skills & Experience
Strong hands-on expertise in Cadence Virtuoso LayoutXL
Solid command of Mentor Calibre (DRC, LVS, extraction, post-layout sims)
Proven experience in FinFET / Planar CMOS (SiGe/GaN is a plus)
Extensive PAD Ring and Chip-Top integration experience (Analog IP + Digital GDS)
Deep understanding of DFM principles
Expertise in high-speed SERDES, RF, and/or PM layouts
If you’ve led complex analog layouts and enjoy building teams as much as silicon, let’s talk.
Share your resume for a deeper discussion.
Chrees,
Shahid