
Proxelera helps semiconductor teams reduce risk and accelerate silicon delivery with end-to-end product engineering. It delivers ASIC/SoC design, RTL, verification, FPGA prototyping, and embedded software, including IP design and post-silicon validation. The company performs physical design, fab interfacing, and silicon productization, leveraging SystemVerilog, UVM, Python, C/C++, Linux, and Yocto. It supports collaboration with hardware teams and offers outcome-based engagements and royalty-based models, serving global semiconductor customers. With over 190 engineers across Bengaluru and Mysuru and global sales in the USA and Japan, Proxelera scales turnkey chip design projects.

Proxelera helps semiconductor teams reduce risk and accelerate silicon delivery with end-to-end product engineering. It delivers ASIC/SoC design, RTL, verification, FPGA prototyping, and embedded software, including IP design and post-silicon validation. The company performs physical design, fab interfacing, and silicon productization, leveraging SystemVerilog, UVM, Python, C/C++, Linux, and Yocto. It supports collaboration with hardware teams and offers outcome-based engagements and royalty-based models, serving global semiconductor customers. With over 190 engineers across Bengaluru and Mysuru and global sales in the USA and Japan, Proxelera scales turnkey chip design projects.
If custom analog layout is your playground and tape-outs are your milestones, this one’s built for you.
Role Scope
Lead end to-end custom layout for Analog/Mixed-Signal IPs and custom-digital blocks in a full SoC flow
Deliver PV-clean layouts with zero surprises at DRC/LVS
Drive floorplanning, routing, matching, parasitic control, signal integrity, power distribution, and area optimization
Review layouts with Analog Design teams and align on trade-offs
Mentor junior layout engineers and set quality benchmarks
Plan schedules and execution strategy in close sync with design teams
Skills & Experience
Strong hands-on expertise in Cadence Virtuoso LayoutXL
Solid command of Mentor Calibre (DRC, LVS, extraction, post-layout sims)
Proven experience in FinFET / Planar CMOS (SiGe/GaN is a plus)
Extensive PAD Ring and Chip-Top integration experience (Analog IP + Digital GDS)
Deep understanding of DFM principles
Expertise in high-speed SERDES, RF, and/or PM layouts
If you’ve led complex analog layouts and enjoy building teams as much as silicon, let’s talk.
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Chrees,
Shahid