
Chip Smart Technologies provides semiconductor design services to build advanced telecom and photonics chips. It focuses on ASIC design with mixed-signal IP, firmware solutions for large telecom systems, RF and photonic ICs, and FPGA capabilities, supported by RTL coding and verification. The company operates as a B2B services firm working with telecoms, semiconductor designers, and embedded systems developers, leveraging standard EDA tools like Cadence, Synopsys, and Mentor Graphics. Its product portfolio includes analog and mixed-signal functional blocks, I/O interfaces, RF blocks, and embedded systems development, including configurable 5G AI Accelerator architectures to boost network performance. Chip Smart Technologies aims to be a leading global chip design company delivering high-quality semiconductor solutions that advance technology and improve lives.

Chip Smart Technologies provides semiconductor design services to build advanced telecom and photonics chips. It focuses on ASIC design with mixed-signal IP, firmware solutions for large telecom systems, RF and photonic ICs, and FPGA capabilities, supported by RTL coding and verification. The company operates as a B2B services firm working with telecoms, semiconductor designers, and embedded systems developers, leveraging standard EDA tools like Cadence, Synopsys, and Mentor Graphics. Its product portfolio includes analog and mixed-signal functional blocks, I/O interfaces, RF blocks, and embedded systems development, including configurable 5G AI Accelerator architectures to boost network performance. Chip Smart Technologies aims to be a leading global chip design company delivering high-quality semiconductor solutions that advance technology and improve lives.
We are looking for Analog Layout Engineer with 2+ Years of experience for the Bangalore Location.
Analog & Mixed-Signal layout implementation of sub-blocks in PLL, SerDes & MIF IPs
Floor planning with a strong focus on area and parasitic optimisation
Layout execution for high-speed block-level and hierarchical designs
Physical verification, including LVS, DRC, and DFM for multi-hierarchical designs
Close collaboration with design and verification teams
🧠 Skill Requirements
Strong hands-on experience in Analog Layout
Expertise in floor planning, routing, matching, and shielding
Good exposure to LVS, DRC, and DFM checks
Understanding of parasitic effects in high-speed designs