Core focus: Accelerated computing and AI infrastructure (GPUs, data center and AI systems, edge/robotics, automotive)
Founded: April 1993
Public company / Investor relations: Maintains an active investor relations portal with quarterly results and presentations
Company Overview
Problem Domain
High-performance graphics, machine learning/AI acceleration, and full-stack AI infrastructure for enterprise, cloud and edge use cases.
Founded
1993
Industry
Semiconductors / AI infrastructure
Tech Stack
GPUs (GeForce, RTX)
AI systems (DGX, NVIDIA AI Enterprise)
Edge/robotics platforms (Jetson, Isaac)
Automotive AI (DRIVE)
AI CPUs (NVIDIA Vera announced)
AI software stacks and libraries
Funding Track Record
Public company / IPO-era financing documented
Historical financing and IPO-related information are documented on financial profiles; NVIDIA also deploys strategic investments in startups (examples reported)
Strategic investments- 2026-01-26
$2B
Reported $2B investment to support CoreWeave's AI compute expansion
Founders
What we do
Join the Team
Analog Digital Mask Design Engineer
On-SiteBengaluru, Karnataka, IN
On-Site • Bengaluru, Karnataka, IN
NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!
We are looking for an Layout Design Engineer– someone who is excited to join a growing group of diverse individuals responsible for handling challenging analog circuit designs. NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence.
What you'll be doing:
Execute IC layout of cutting edge, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 2nm, 3nm, 5nm, 7nm and lower nodes following industry best practices.
Deliver layouts for Circuit Solutions Group specializing in digital cum analog IPs.
IP layout will comprise of significant digital components and some analog components.
Adopting and putting in place best layout practices/methodology for composing Analog and digital layouts
What we need to see:
4+ years of experience in high performance analog layout in advanced CMOS process.
BE/M-Tech in Electrical & Electronics or equivalent experience.
We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.
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Follow company procedures and practices for IC layout activities.
Perform full custom layout of analog/mixed-signal blocks such as op-amps, bandgaps, PLLs, ADCs, DACs, LDOs, Voltage Regulators etc.
Ensure design quality by adhering to matching, symmetry, and parasitic sensitivity requirements.
Optimize layouts for area, performance, and manufacturability.
Thorough knowledge of industry standard EDA tools for Cadence.
Experience with layout of high-performance analog blocks such as Current mirrors, Sense Amps, bandgaps etc. is required.
Knowledge in analog design and layout guidelines, high speed IO, (matching devices, symmetrical layout, signal shielding, other analog specific guidelines)
Experience with floor planning, block level routing and macro level assembly.
Knowledge of high-performance analog layout techniques such as common centroid layout, matching, symmetrical layout, signal shielding, use of dummy devices, thermal aware layout with consideration for electro migration and other analog specific guidelines.
Demonstrated experience with analog layout for silicon chips in mass production.
Background with sub-micron design in foundry CMOS nodes 7nm finfet and below is preferred.
Experience working in distributed design team is a plus.
Requires self-starter with the ability to define and adhere to a schedule.
