Role & responsibilities :-

• Lead design of analog IPs PLLs, Bandgaps, LDOs, ADCs, DACs, amplifiers, oscillators, etc.
• Own end-to-end design: specs circuit design simulation layout post-layout silicon.
• Perform PVT, Monte Carlo, noise, jitter, and reliability analysis.
• Guide layout engineers and collaborate across design, AMS, and system teams.
• Support silicon bring-up, debug, and characterization.
• Mentor junior engineers and drive design best practices.

Preferred candidate profile :-

• 2+ years of experience in analog/mixed-signal circuit design.
• Strong CMOS fundamentals and hands-on experience with Cadence/Spectre/HSPICE.
• Proven tape-out and silicon validation experience.
• Expertise in core analog building blocks and modeling (Verilog-A/AMS).