Responsibilities

• Serve as the technical authority for pixel reconstruction algorithms, influencing imaging architecture decisions across ISP, sensor, optics, and AI imaging pipelines, and driving improvements in end-user perceptual video quality and overall camera experience.

• Collaborate closely with cross-functional teams to develop proposals for next-generation imaging solutions in the domain of pixel reconstruction, addressing customer requirements and limitations of existing approaches

• Define and drive the roadmap for core computational imaging algorithms (e.g., denoising, super-resolution, bokeh, multi-frame fusion), ensuring continuous product competitiveness in image quality and user experience

• Propose efficient HW IP / SoC architecture solutions through detailed analysis of power, performance, area, latency, and image quality trade-offs

• Lead the end-to-end validation of pixel reconstruction innovations, from concept exploration and simulation to prototype implementation and performance benchmarking, guiding the overall algorithm development strategy

• Continuously evaluate and integrate state-of-the-art algorithms relevant to embedded imaging systems, image processing, and video processing

• Mentor senior engineers and collaborate across global multidisciplinary teams, including ISP architecture and design, sensor development, and product engineering.

Requirements

• Master’s or PhD degree in Electrical Engineering, Computer Vision, Computational Imaging, or a related field, with 15+ years of industry experience in mobile imaging systems.

• Deep expertise in mobile imaging systems and camera module design, including image sensors, optics, mechanics, auto-focus systems, optical image stabilization, and both software and hardware image processing pipelines

• Proven experience designing and deploying modern computational imaging algorithms, such as denoising, super-resolution, bokeh/depth rendering, and multi-frame image fusion

• Strong experience optimizing imaging algorithms for embedded hardware platforms, considering constraints such as power consumption, performance, memory bandwidth, silicon area, and latency

• Demonstrated leadership experience, including mentoring senior engineers and driving cross-functional collaboration across globally distributed teams.