AI Data Center High-Speed Interconnect Architect

Location : Bay Area strongly preferred – maybe Seattle WA / Austin TX

Job Summary:

The High-Speed Interconnect Architect will define and engineer the architecture for

advanced high-speed interconnect systems integral to next-generation AI servers and rack

configurations. This entails the development of technologies such as high-speed backplanes

(NVLINK, UALINK), co-packaged copper, high-speed cables, PCIe, CXL, OSFP, OSFP-X,

448G/lane technology, and sophisticated onboard connectors. The architect will ensure these

solutions satisfy stringent demands for bandwidth, latency, signal integrity, scalability, and

reliability within high-density AI and HPC environments. This position necessitates close

collaboration with interdisciplinary teams and active participation in industry standardization

bodies to propel innovation and adoption. This role is crucial for the realization of next-

generation scalable, high-performance AI infrastructure through advancements in

interconnect technology.

Essential Duties and Responsibilities:

 Architectural Design and Optimization: Architect and optimize high-speed

interconnect solutions, including backplanes, co-packaged copper, cables, OSFP,

OSFP-X, and onboard connectors, for AI/ML and HPC platforms. Achieve equilibrium

among performance, signal integrity, power consumption, cost efficiency, and

manufacturing feasibility.

 Technology Assessment: Lead the assessment and selection of interconnect

technologies (e.g., NVLINK, UALINK, PCIe, CXL), considering evolving standards

and future scalability imperatives.

 Signal and Power Integrity Management: Collaborate with signal and power integrity

engineers to ensure robust high-speed data transmission and adherence to electrical

and EMI/EMC standards.

 Interdepartmental Collaboration: Engage with hardware, system, packaging, and

software development teams to integrate interconnect solutions into AI server and

rack architectures.

 Industry Standards Participation: Represent the organization in standards bodies

(e.g., OCP, PCI-SIG, UALINK, IEEE, CXL Consortium), influence the formulation of

next-generation interconnect standards, and monitor industry trends.

 Client and Partner Liaison: Interact with hyperscalers, OEMs, and technology

partners to ascertain requirements, address challenges, and facilitate the

collaborative development of innovative solutions.

 Technical Documentation and Strategic Planning: Author technical specifications,

architecture documents, and contribute to the product roadmap for high-speed

interconnects.

Requirements

 Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a

related discipline.

 Minimum of 5-10 years of professional experience in high-speed interconnect

architecture, signal integrity, or system design for compute, networking, or AI

platforms.

 Extensive expertise in high-speed protocols (NVLINK, UALINK, PCIe, CXL, Ethernet,

InfiniBand, OSFP, OSFP-X) and advanced connector/cabling technologies.

 Comprehensive knowledge of signal integrity, power integrity, PCB/package/system

design, and relevant simulation tools.

 Proven experience in participating in or influencing industry standards development.

 Exceptional communication and cross-functional leadership proficiencies.

 Familiarity with hardware/software co-design and performance analysis for AI/HPC

workloads is advantageous.