What You Will Do

• Architect the Vision Chip: Design and implement FPGA-based architectures to accelerate core spatial tasks: depth estimation, feature tracking, and point-cloud processing.
• Hardware-Accelerated SLAM: Port, optimize, and "harden" state-of-the-art SLAM algorithms (e.g., ORB-SLAM, VIO, LOAM) from C++ into RTL (Verilog/VHDL).
• Sensor Fusion at the Edge: Develop high-speed data pipelines to fuse multi-modal inputs (LiDAR, Stereo, IMU) directly on the FPGA to achieve sub-millisecond latency.
• AI-Hardware Co-Design: Collaborate with our AI team to optimize 3D neural networks (like PointNet++ or 3D Segmentation) for deployment on custom hardware.
• RTL to Reality: Manage the full FPGA lifecycle—from HLS prototyping and RTL coding to timing closure, verification, and on-device deployment.

Who You Are

• The Bridge: You can read a SLAM research paper and visualize exactly how those matrix operations should be pipelined in hardware.
• FPGA Power User: Mastery of Verilog/VHDL and toolchains like Xilinx Vivado or Intel Quartus . Experience with HLS (High-Level Synthesis) is a major plus.
• 3D Geometry Expert: Deep understanding of the math that powers vision—quaternions, transformation matrices, epipolar geometry, and Kalman filters.
• C++ Expert: Strong proficiency in modern C++ and experience with libraries like OpenCV, PCL, or Eigen .
• Experience: 3+ years in computer vision or robotics, with a proven track record of deploying algorithms on embedded hardware or FPGAs.

To stand out for the 3D Spatial Vision Intelligence Engineer role at Luxolis , candidates must possess a "Full-Stack Hardware" mentality. This means combining the high-level mathematical theory of 3D geometry with the low-level constraints of RTL and digital logic.

Below are the detailed qualifications categorized by priority.

Educational Background

• Minimum: Bachelor’s or Master’s degree in Electrical Engineering (EE), Computer Engineering (CE), Robotics , or a related field.
• Preferred: A PhD with a research focus on Computational Imaging, SLAM, or Hardware Acceleration for Computer Vision.
• Key Coursework: Digital Logic Design, Computer Architecture, Linear Algebra, Probability & Stochastic Processes, and Computer Vision.

Technical Skills: The "Spatial Intelligence" Stack

These are the core competencies required to design a chip that "sees" and "understands" 3D space.

1. SLAM & 3D Perception

• Algorithmic Expertise: Deep understanding of Visual-Inertial Odometry (VIO) , LiDAR SLAM (e.g., LOAM, LeGO-LOAM), and Visual SLAM (e.g., ORB-SLAM3).
• Geometric Math: Mastery of SO(3) and SE(3) Lie Groups , quaternions, epipolar geometry, and bundle adjustment.
• State Estimation: Hands-on experience with Extended Kalman Filters (EKF) , Unscented Kalman Filters (UKF), and Factor Graph Optimization (GTSAM/Ceres).

2. FPGA & RTL Engineering

• Hardware Description Languages: Expert-level Verilog or SystemVerilog (preferred) or VHDL.
• Design Tools: Proficiency in Xilinx Vivado , Intel Quartus, and High-Level Synthesis (HLS) for rapid algorithm prototyping.
• Architectural Knowledge: Experience with AXI protocols , DMA, and memory controllers (DDR4/HBM) to handle high-bandwidth 3D point cloud data.
• Verification: Experience with UVM/OVM or hardware-in-the-loop (HIL) testing to ensure "first-time-right" silicon logic.

3. Software & Optimization

• Primary Languages: High proficiency in Modern C++ (14/17/20) for performance-critical systems and Python for algorithm modeling.
• Vision Libraries: Strong experience with OpenCV , PCL (Point Cloud Library) , and Eigen.
• Acceleration: Familiarity with SIMD instructions or CUDA (for benchmarking FPGA performance against GPU equivalents).