FuriosaAI

FuriosaAI is an AI chip company developing data center accelerators focused on efficient AI inference for large language models (LLMs) and multimodal applications. Their flagship product, RNGD (Gen 2), is designed with a proprietary Tensor Contraction Processor (TCP) architecture to achieve high performance and efficiency, targeting lower total cost of ownership. The company also offers the Gen 1 Vision NPU for computer vision tasks. FuriosaAI provides a comprehensive software stack, including the Furiosa SDK, to optimize and deploy AI models. They emphasize programmability, efficiency, and ease of use, aiming to make AI computing more sustainable. The company has a global presence with R&D headquarters in Seoul, Korea, and hubs in the US and Germany.

AI AcceleratorsData CenterEfficiencyFull-Stack AILLM InferenceNPUSustainabilityTensor Contraction Processorfuriosa.ai

FuriosaAI

AI AcceleratorsData CenterEfficiencyFull-Stack AILLM InferenceNPUSustainabilityTensor Contraction Processorfuriosa.ai

HQUndisclosed

Team Size154

Open Jobs40

Total Funding$266M

Latest Fundraise8 months ago

Join the Team

NPU MI (Management Interface) Software Engineer

On-SiteSeoul, Seoul, KR

On-Site • Seoul, Seoul, KR

Teeming tracks opportunities at over 24,000 AI startups, then works with you to find (and land) the one you'll love.

Technical Writer

ContractRotterdam, NL

Contract • Rotterdam, NL

Backend Developer

Full-timeNew York, US

Full-time • New York, US

DevOps Engineer

Full-timeCambridge, GB

Full-time • Cambridge, GB

Mobile Developer

InternshipNovi Sad, RS

Internship • Novi Sad, RS

Product Designer

Part-timeBerlin, DE

Part-time • Berlin, DE

Data Scientist

InternshipAmsterdam, NL

Internship • Amsterdam, NL

Responsibilities

Design and develop the NPU Management Interface (MI) firmware/software enabling communication between Host/BMC and NPU devices
Implement and maintain MCTP, PLDM, and custom MI command handling for out-of-band NPU management, monitoring, and control
Develop device-management features over SMBus/I²C, I3C, PCIe VDM, or custom sideband channels
Integrate MI functionality into the NPU firmware, including:
Health and error reporting
Thermal and power telemetry
Runtime status, utilization metrics, and debug information
Ensure compliance with industry specifications by performing spec-driven design, implementation, and validation
Support bring-up, interoperability testing, rack-scale platform integration, and system-level validation
Develop test strategies and validation tools based on MCTP and PLDM specifications
Perform protocol compliance testing, regression testing, and interoperability verification

Requirements

Strong proficiency in embedded C or C++
Experience with firmware development for NPU/accelerator, GPU, or SoC
Understanding of management protocols including MCTP (over I²C/SMBus, I3C or PCIe VDM) and PLDM
Experience with low-level interfaces: SMBus/I²C, I3C, SPI, PCIe
Ability to interpret complex protocol specifications and convert them into robust implementations
Familiarity with device telemetry, sensor frameworks, watchdog/reset flows, and health monitoring
Experience with system-level debugging using logic/protocol analyzers and low-level debug tools
Knowledge of embedded systems, bare-metal or RTOS environments, and firmware lifecycle flows

Preferred Qualifications

Experience of BMC firmware stacks such as OpenBMC, Redfish, IPMI, and PLDM device-model implementations
Background in spec creation, requirement definition, or standards compliance validation
Experience defining FRU data, power/thermal management policies, and diagnostics frameworks
Familiarity with secure provisioning, firmware update mechanisms, and lifecycle state management
Experience with large-scale datacenter or HPC system integration (rack-level management, telemetry aggregation)
Contributions to firmware for accelerator, MCTP/PLDM implementations, or open-source system firmware projects

Contact

recruit@furiosa.ai