Partcl
We build GPU accelerated tools for chip designers. Our Electronic Design Automation (EDA) tools offer 1000x runtime improvements without degrading the quality of the output, thus achieving faster time to tapeout.
Partcl
We build GPU accelerated tools for chip designers. Our Electronic Design Automation (EDA) tools offer 1000x runtime improvements without degrading the quality of the output, thus achieving faster time to tapeout.
TL;DR
What they do: GPU-accelerated EDA tools for chip designers, claiming up to 1000x runtime improvements
Stage & funding: Pre-Seed; 1 disclosed round
Investors: Pioneer Fund; Y Combinator
Founders: William Salcedo (Co-founder & CEO); Vamshi Balanaga (Co-founder & CTO)
Location (reported): San Francisco, California
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Company Overview
Problem Domain
Electronic design automation (chip design and timing analysis)
Industry
Semiconductor / EDA
Tech Stack
Funding Track Record
One disclosed round; investors listed include Pioneer Fund and Y Combinator
Investor Signal
“Pioneer Fund; Y Combinator”